Have a great day,
T1040 Data Sheet also says “This pull-up is designed such that it can be overpowered by an external 4.7 k resistor. However, if the signal is intended to be high after reset, and if there is any device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed”
I.e. if the cfg pin will not open the datasheet Require for an external pull-up or active driver. So actual characteristic of the internal pull-up is 4.7k value for external pull-down. They guaranteed that 4.7k pull-down sets the cfg pin to '0', while open cfg pin will have the high level '1'.
I think your question is a question for design group. At least I've never seen such data. Here just some speculations:
* For low level threshold ViL= 0.54V at 1.8V, neglecting by input current we get that weak pull-up has to be greater than 11 k { 1.8*4.7/(4.7+11)=0.539 }.
* If we consider input as 2 resistors of 36k connected to the gnd and 1.8V for the max input current -\+ 50uA (specified in the data sheet) then we get that the weak pull-up has to be less than 36k in order to reach Vih=1.2V at 1.8V {1.8*36/(36/2+36)=1.2 }. If we take 50uA as input current at 1.2V than we get that pull-up has to be less than 12k {(1.8-1.2)/0.05=12} which I consider as unrealistic.
So ~20k is good value for the internal pull-up which should be inside 15k - 35 k
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