Disabling Cores 1,2 and 3. on T1042

[nakrachi]

Hi Everyone,

We are porting our RTOS to the T1042 target and I am wondering how to disable the Cores 1,2 and 3. 

From what I understood from the reference manual, this can be done by configuring (DCFG_CCSR_COREDISR). but this can only be done when the core is in boot-holdoff mode. 

The other way would be setting RCW bit BOOT_HO , but we know that u-boot releases the other cores , the value of DCFG_CCSR_BRR is 0xF after u-boot .

My question is there any way to properly disable the other cores if they are already started ?

p.s : I tested the DCFG_CCSR_COREDISR option, and I confirm that the other cores are not executing any instructions and the timebase is not incrementing. but I want to confirm if it's a proper way to effectively disable the other cores. 

thank you

ZN

[nakrachi]

thanks a lot.

(EDITED)

so u-boot is writing to DCFG_CCSR_COREDISR while cores are not in boot holdoff mode, which contradicts the documentation.

so if my understanding is correct, we can stop the other cores with our Kernel at startup ?

[ufedor · Accepted solution]

> if my understanding is correct, we can stop the other cores with our Kernel at startup ?

Yes.

According to the U-Boot code the RM requirement can be relaxed.

[nakrachi]

Thank you

[ufedor]

In the recent SDK, the dynamic boot up mode is used, you could use the u-boot command "cpu <num> disable" to disable the specific cores, for example if you only want to use core0, you could use the following commands, then boot up kernel:
=>cpu 1 disable
=>cpu 2 disable
=>cpu 3 disable

Actually U-Boot "cpu <N> disable" sets corresponding bit in the DCFG_CCSR_COREDISR.