I have an existing kernel module that checks L2 cache for tag/data errors. This works well on a T1042 (e5500). On the e5500, the L2 registers are implemented as special purpose registers so the module simply reads/tests the required SPR's. I am now needing to do this same functionality on a T2080 (e6500). The L2 registers on the e6500 are no longer implemented as SPR's but are located in the CCSR space. How do I access the shared L2 cluster registers from my existing driver. I tried reading the SCCSRBAR and shiting left 24 bits and then adding the cluster offset. This yields:
Unable to handle kernel paging request for data at address 0x7200c20000
Questions:
(1) Is there an exiting driver already included in the QorIQ_SDK_2.0 that I could use to access these registers from user-space? This must surely be supported by the SDK for the SoC. I would prefer this method and just do my L2 checks from a user-space app.
(2) If not, what is the recommended way to access registers in the CCSR space? mmap from user-space app I presume?
Any suggestions appreciated.
