Hi,
Our serdes protocol is 0x87.
We intend to configure serdes lane D in 1000Base-KX, i.e mac-2 which is SGMII 1G by default.
As per T1040 Manual Sec: 31.6.1.3 1000Base-KX, settings have been made.
Here we have these doubts:
1. To access clause45 registers of 1000BAse-KX:
SGMIInCR1[MDEV_PORT] is set 0, MDIO_CTL[PORT_ADDR] is aslo set 0. Is it correct?
2. 1000Base-KX (Clause 45) AN Advertisement Register 1, TX_NONCE=unique value per device;
so we set TX_NONCE 0xF and 0xC for two devices which are connected via 1000Base-KX through Backplane. Is it correct?
Result:
We are able to ping from one board to the other via this interface.
However, the 1000Base-KX (Clause 45) AN Status Register = 0x8, i.e LNK_STAT is 0 so link is down.
Also we noted that the interfaces were able to ping, even before setting AN Advertisement Register 1 and AN Control Register (i,e steps 5 to 9 of sec: 31.6.1.3)
Thanks
Debdutta
These are the steps :
1. SerDes_LNnGCR0[TRST_B(9),RRST_B(10)] = 00,
where, SerDes_LNnGCR0=0xffe000000+0xEA000+0x800+(64*serdes_no), serdes_no=3 for lane-D
2. SerDes_LNnGCR1[REIDL_TH(9-11)]=000
SerDes_LNnGCR1[REIDL_EX_MSB(16),REIDL_EX_SEL(12,13)]=000
SerDes_LNnGCR1[REIDL_ET_MSB(17),REIDL_ET_SEL(14,15)]=000,
where, SerDes_LNnGCR1=0xffe000000+0xEA000+0x804+(64*serdes_no)
3. SerDes_LNnTECR0[AMP_RED(26-31)]=00_0000,
where, SerDes_LNnTECR0=0xffe000000+0xEA000+0x818+(64*serdes_no)
4. SerDes_LNnGCR0[TRST_B(9),RRST_B(10)] = 11
5. SerDes_PLLnCR0[DLYDIV_SEL(30,31)]=01, where, SerDes_PLL0CR0=0xffe000000+0xEA000+0x4
6. SerDes_PCCR1[SGMIIn_KX(17)]=1, where, SerDes_PCCR1=0xffe000000+0xEA000+0xE4
7. SerDes_SGMIInCR1[MDEV_PORT]=0, where, SerDes_SGMIInCR1=0xffe000000+0xEA000+0x604+(16*1)
8. MDIO_SGMII_IF_MODE=0x0008, following T1040DPAARM sec: 6.5.5.4 Clause 22 Write Flow
here, MDIO_CTL is initialized with PHY_ADDR=0.
9. Read 100Base-KX PCS MDIO_SGMII_IF_MODE reg to verify it is initialized to 0x0008
9. MDIO_KX_AN_ADVERT1[TX_NONCE]=0xF, and 0xC for the other board
10. Read MDIO_KX_AN_SR
11. MDIO_KX_AN_CR=0x1200
to set MDIO_SGMII_IF_MODE=0x0008:
For Serdes lane-D, corresponding mac is 2
1. MDIO_CFG[ENC45]=0, where MDIO_CFG=0xFFE000000+0x400000+0xE3000+0x30
2. Wait for MDIO_CFG[BSY] = 0
3. MDIO_CTL=0x14, where MDIO_CTL=0xFFE000000+0x400000+0xE3000+0x34
here PHY_ADDR=0, REGISTER_ADDR=0x14 (MDIO_SGMII_IF_MODE)
4. MDIO_DATA=0x0008, where MDIO_DATA=0xFFE000000+0x400000+0xE3000+0x38
For both the boards connected via 1000Base-KX through backplane the same steps are followed except MDIO_KX_AN_ADVERT1[TX_NONCE]=0xC in one and MDIO_KX_AN_ADVERT1[TX_NONCE]=0xF in the other.
To set MDIO_KX_AN_ADVERT1:
1. MDIO_CFG[ENC45]=1
2. wait for MDIO_CFG[BSY] = 0
3. set MDIO_CTL=0x7 , here, PORT_ADDR=0, DEV_ADDR=7
4. MDIO_ADDR=0x11 (MDIO_KX_AN_ADVERT1), where MDIO_ADDR=0xFFE000000+0x400000+0xE3000+0x3C
5. Wait for MDIO_CFG[BSY] = 0
6. MDIO_DATA=0xF
Hi,
this step was not done correctly:
5. SerDes_PLLnCR0[DLYDIV_SEL(30,31)]=01, where, SerDes_PLL0CR0=0xffe000000+0xEA000+0x4
Instead of SerDes_PLL0CR0=0xffe000000+0xEA000+0x4 for PLL0, we were actually configuring:
SerDes_PLL0CR1=0xffe000000+0xEA000+0x4+(32*1) for PLL1.
After making this correction we are able to get proper link status in:
1000Base-KX (Clause 45) AN Status Register = 0x2d
I hope this means that our 1000Base-KX link is up and running?