SM3.RESET_MON

[HeebeomPark]

The following is the description of SM3.RESET_MON.

"External Reset Monitoring Off-chip hardware provides monitoring of the reset signal of the MCU to detect multiple reset cycling. The MCU can program the threshold value for this counter in off-chip hardware.
The off-chip hardware also controls the chip's reset input/output to ensure correct reset assertion without any glitches being injected in the MCU .

Reaction:
This is provided by an assumption in Safety Manual." 

The mechanism is to monitor the status of the reset pin of MCU, in case of any glitch of the reset pin line? Or it is to monitor the continuous reset occur by MCU itself?

In case any malfunction situation is detected, the expected reaction from PMIC is to trigger the reset to MCU correctly? Otherwise, what are the reaction of the SM3.RESET_MON?

[nxf55526]

Hi HeebeomPark,

SM3.RESET_MON detects when the chip is in reset and in case the chip has been going through reset cycling, it can power-down the chip. Also, as part of this safety mechanism, the off-chip hardware initiates a chip reset when required. To fulfill this safety mechanism, you need to fulfill the following Assumptions of use present in the safety manual : 1222001, 59458 and 7501. 

Kind Regards,

Avni