[SM_213] PLL configuration check, S32K146

[yin_hua]

Hello NXP,

I'm confused about SM_213, please help to clarify.

1. According to the safety manual, the S32K146 MCU is utilized with clock monitor for SOSC and PLL, why this additional PLL check in SM_213 is required? 

2. SM_213 is written under "initial checks and configurations" section, which means NXP assumes this check shall be performed at start up to detect latent fault, but actually the SPLL lock failure is single point fault, then SM_213 shall be defined as run time check, please help to clarify.

Thanks

Yin Hua

[jinjingyang]

Hi,

I think it's because SPLL can detect loss of lock failure, but cannot detect SPLL frequency inaccuracy or frequency variation failure. So it's good practice to measure the SPLL frequency with a different timer running on XOSC or FIRC to make sure the SPLL output frequency is accurate.

[yin_hua]

Hi Jason Yang,

As written in safety manual 5.3.3, 

The S32K14x and S32K14xW includes clock monitors for the SOSC and SPLL. The clock monitors use the SIRC (8 MHz internal oscillator) as the reference clock for independent operation from the monitored clocks. Their purpose is to check for error conditions due to:
• loss of clock from external crystal (SOSC)
• SPLL clock out of a programmable frequency range (frequency too high or too low -loss of clock)
• loss of SPLL clock

1. The frequency inaccuracy is also included in S32K14x clock monitor. Therefore I'm still confuse about the necessity of SM_213

2. Could you please also explain the reason why in SM_213 is not defined as runtime check? 

[aarul]

Hello Yin Hua

The reason this is a requirement to check at startup is because after you enable a PLL, it takes certain time to achieve lock. This check ensures that PLL has locked and it is OK to enable PLL monitor. If you enable the PLL monitor, without doing this check you will either get false errors or no error even if PLL is out of range as the PLL monitor may not work.

Hope this helps,

Regards

-Aarul Jain