S32K344 Static FMEDA, Safety Mechanisms and ASIL

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S32K344 Static FMEDA, Safety Mechanisms and ASIL

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FabioG
Contributor III

Hi  There 

Regarding S32K344 FMEDA in "S32K344_172Pins_2023_R1.003.xlsx" file I understand, correct me if I am wrong:

1)in order to reach the metrics in "Metrics tab" we must implement ALL Safety mechanisms listed in "Safety Mechanism Tab" isn't it?

2) The metrics listed in "Metrics" tab is related to an ASIL D safety integrity level ;isn't it?

3) so (from point 2) it is implicit that FHTI to get that metrics is <=10 ms (Asil D) isn't it?

4) and (from point 2) s32k344 is in lockstep mode (ASIL D)  to reach that metrics isn't it?

5) if we use an s32k344 in performance mode (independent cores ), the safety integrity level is ASIL B and we dont have any FMEDA in support so we should ask to NXP an help to a new FMEDA, isn't it?

6) If we use a lockstep S32K344 microcontroller, we should implement all SM to reach an ASIL D safety integrity level . If we decide to get an ASILB safety integrity level for our system  we need to contact NXP to get another FMEDA., isn't it?

Best regards

Fabio

 

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Yashwant_Singh
NXP Employee
NXP Employee

Hello,

Apologies for the delay.

1)There are the following criteria of safety mechanisms involved.

SM1 Hardware safety mechanism within the chip, implemented by NXP
SM2 Software safety mechanism specified for the chip, implemented by NXP (SAF)
SM3 Off-chip hardware safety mechanism, to be implemented by the
system developer

SM4 Software safety mechanism, to be implemented by the system developer

The safety mechanism which are to be implemented by the system developer are linked with the relevant AoUs or Assumption on Use.

An Aou is a hardware or software functional-safety requirement at the level of the system into which an
NXP product is to be integrated. When developing a product, NXP makes specific assumptions
about the intended functionality and use context, which includes external interfaces.
There is a specific set of assumptions, see the related description in the 'Addendum Worksheet' attached with the device's safety manual

2) Yes the metrics listed in "Metrics" tab is related to an ASIL D safety integrity level.

3) Yes the FHTI to get that metrics is <=10 ms (Asil D) 

4) Yes S32K344 is in lockstep mode (ASIL D)  to reach that metrics.

5) Yes we can generate an FMEDA for S32K344 running in split lock or performance mode with the mission profile and peripheral usage applicable as per your use case.

6) Yes as stated in point 5 we will generate another FMEDA for ASIL B (splitlock/performance) use case.

Hoping this helps!

Thanks!

-Yashwant

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Yashwant_Singh
NXP Employee
NXP Employee

Hello,

Apologies for the delay.

1)There are the following criteria of safety mechanisms involved.

SM1 Hardware safety mechanism within the chip, implemented by NXP
SM2 Software safety mechanism specified for the chip, implemented by NXP (SAF)
SM3 Off-chip hardware safety mechanism, to be implemented by the
system developer

SM4 Software safety mechanism, to be implemented by the system developer

The safety mechanism which are to be implemented by the system developer are linked with the relevant AoUs or Assumption on Use.

An Aou is a hardware or software functional-safety requirement at the level of the system into which an
NXP product is to be integrated. When developing a product, NXP makes specific assumptions
about the intended functionality and use context, which includes external interfaces.
There is a specific set of assumptions, see the related description in the 'Addendum Worksheet' attached with the device's safety manual

2) Yes the metrics listed in "Metrics" tab is related to an ASIL D safety integrity level.

3) Yes the FHTI to get that metrics is <=10 ms (Asil D) 

4) Yes S32K344 is in lockstep mode (ASIL D)  to reach that metrics.

5) Yes we can generate an FMEDA for S32K344 running in split lock or performance mode with the mission profile and peripheral usage applicable as per your use case.

6) Yes as stated in point 5 we will generate another FMEDA for ASIL B (splitlock/performance) use case.

Hoping this helps!

Thanks!

-Yashwant

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