Hello, team,
According to S32K3 safety manual and RM, there is "EDC after ECC" feature for S32K3 SRAM.
S32K3 Safety Manual section 5.2.2.6:
" It is worth to note that this observation cannot verify the correct function of the correction by the ECC safety mechanism in absence of a fault; for this purpose an error injection (for example—by the EIM) may be required."
The question is:
1) What register bits are used to indicate EDC after ECC fault?
I guess it's DCMROD4 bit9 (PRAM0_FCCU_ALARM) and bit10 (PRAM1_FCCU_ALARM).
Could you please confirm whether it's correct or not?
2) What is the suitable way to inject EDC after ECC fault?
I can inject RAM ECC fault and detect the fault. Flags can be read in ERM, FCCU, DCMROD3~5 registers. But I can see only RAM ECC fault not EDC after ECC fault.
And I can call the SPD API function
"eMcem_InjectFault( EMCEM_DCM_NCF_2_PRAM0_AHB_ALARM );"
to inject a PRAM0_AHB_ALARM fault. But this way only inject fault to FCCU NCF2. It doesn't inject real fault and the DCMROD4 register bit is not set.
Is there are way to inject an EDC after ECC fault?
