S32K memory failure rate in high altitude

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S32K memory failure rate in high altitude

684 次查看
sfjia
Contributor II

Hi

We have talked about questions of working altitude. And the discussion is marked as solved. As below:

https://community.nxp.com/t5/SafeAssure-NDA-group/Altitude-requirement-considering-MCU-soft-error/m-... 

Our product may working in altitude upto 4800m.

Pls help to provide the failure rate or FMEDA in this condition. (Considering that altitude>2000m,the soft-error rate shall be increased by a appropriate factor according to e.g. JESD89A.)

Thanks

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681 次查看
aarul
NXP Employee
NXP Employee

Hi

Can you please provide the exact product name in the S32K1xx family?

Regards

-Aarul

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677 次查看
sfjia
Contributor II

Hi Aarul

It's S32K144 

Thanks

Sifeng

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657 次查看
aarul
NXP Employee
NXP Employee

Hi

For an altitude of 4800m the FIT rate increases by a factor of about 15. (exact 15.147...).

Hope this answers your question.

Regards

-Aarul

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655 次查看
sfjia
Contributor II

Hi Aarul

Thanks.

Does it mean Initial FIT(sea level)*15.147?

Is it same for both SRAM and Flash?

 

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647 次查看
aarul
NXP Employee
NXP Employee

Yes, initial FIT(sea level)*15.147

This is for SRAM only. For Flash, the design is robust to transient failures and hence flash remains unaffected due to altitude.

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643 次查看
sfjia
Contributor II

Hi Aarul

Thanks for answer.

Our project is in certification process by TUV.

They have two concern:

1. How does NXP get the factor(15.147 on 4800m)? Is it based on any standard(which standard)?

2. Why Flash doesn't need to consider transient failures? TUV think the "soft error" will increase anyhow in high altitude. what's the robust design of S32K144?

Need your help!

Thank you!

 

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631 次查看
aarul
NXP Employee
NXP Employee

1. The failure rates at sea-level are based on measurements performed in compliance with JESD89A. The scaling factor for the neutron flux is calculated at http://www.seutest.com/cgi-bin/FluxCalculator.cgi. JESD89A refers to this link for the neutron flux calculation.

 

2. To my best knowledge, flash bit cells are not sensitive to soft-error due to technology (low density planar embedded NVM ) used by NXP. During testing state change of bit cells was not observed. Please also note that irrespective of this we do have ECC correction logic on Flash which can correct any error at higher altitudes. So there shouldn't be any safety issues to assessor.

Regards

-Aarul

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