Hi NXP,
I have a question regarding NXP S32G274, for the SRAM ECC.
According to S32G2 Reference Manual, Section 35.2.2 Features (for SRAM Controller), the SRAMC features include:
- SRAM data is covered by 8-bit ECC on a 64-bit basis using the H-matrix that includes address in the syndrome calculation, which enables single-error correction, double-error detection (SECDED)
According to S32G2 Safety Manual, Section 1.4.6.2 SRAM monitoring requirements:
- Safety-related SRAM should use ECC to detect and correct faults (SEC/DED).
- Correctable errors shall be corrected transparently.
But according to S32G2 Safety Manual "Addendum_S32G2.xlsx", Assumption "27102":
"The application software periodically—at least once per drive cycle—checks all the ERM module's ECC correctable error counters and reacts as follows:
- If a counter is 0, does nothing.
- If a counter is greater than or equal to 1, where possible within the application and memory location, corrects the memory location by performing a read, writes back the read data, and then reads the memory location again. The application software then checks that the counter value shows that the error was corrected, and then resets the counter by writing all zeros."
My understanding is that SRAM Controller will perform ECC (SECDED) automatically per SRAM word (64-bit data, 29-bit address, 8-bit CRC). Therefore, any ECC single bit error should be corrected automatically. But the assumption "27102" suggests that application SW is responsible to trigger ECC single-bit error corrections.
Which is correct?
Kind Regards, Manny.
