ADC failure modes for S32K146

[yin_hua]

Hi NXP,

I'm checking the S32K146 FMEDA in peripheral sheet, it is defined as follow:

ADC0-1	Combinatorial Logic Gates: Stuck-at
	Flip-Flops: Stuck-at
	Analog Gate Equivalents: Stuck-at
	Flip-Flops: Single event upset

It is impossible to use these failure modes in application level FMEDA to analysis ADC. Could NXP provide the failure modes for ADC port defined in the failure effect way (e.g. stuck at valid range, drift, open, short.etc). 

Similarly, could NXP also provide the pin failure in the failure effect way (e.g. open, short.etc)

[aarul]

Hi

We would recommend to analyze the effect of ADC failures at system level based on your application use-case of ADC.

You can refer to Table 36, in ISO26262:2018-Part 11 if you wish to look at something between the low level failure modes described in NXP FMEDA or the failure modes you may want to describe in  your System Level FMEDA. In general, the effect of either of these failure modes is incorrect conversion.

For Pin, we have an example in the Peripheral FMEDA for the failure modes of the Pin (short and open).

Regards

-Aarul

[yin_hua]

Hi aarul,

It is possible to define failure modes according to application refer to ISO26262, but still the failure modes distribution is difficult to judge. Also does the assumed failure modes make sense will lack of evidence since I can't judge the real failure effect which could be seen in system level due to internal failure of ADC (e.g. gate failure). It will be appreciate that NXP could provide the recommend failure modes and distribution by linking the internal ADC failure modes and failure effect which could be seen by system with d.c.fault model

Looking for your support.

[aarul]

Hi

Please find attached some more information on this based on internal discussion. We hope this is what you are looking for.

Regards

-Aarul