s32k spi send message

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s32k spi send message

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liulei1
Contributor II

I want to send a message, but the oscilloscope can only see CS pull low and CLK waveform, SIN and SOUT have no waveform.

uint8_t OLA_SDK_LPSPI_WirteRead(LPSPI_Type * base,uint8_t Send_Value)
{
uint8_t DataValue = 0;

while(!(LPSPI_GetStatusFlag(base,LPSPI_TX_DATA_FLAG))); /* Wait for Tx FIFO available */
LPSPI_WriteData(base,Send_Value); /* Transmit data */
LPSPI_ClearStatusFlag(base,LPSPI_TX_DATA_FLAG); /* Clear TDF flag -- LPSPI1->SR |= LPSPI_SR_TDF_MASK; */

while(!(LPSPI_GetStatusFlag(base,LPSPI_RX_DATA_FLAG))); /* Wait at least one RxFIFO entry */
DataValue= LPSPI_ReadData(base); /* Read received data */
LPSPI_ClearStatusFlag(base,LPSPI_WORD_COMPLETE); /* Clear RDF flag */
LPSPI_ClearStatusFlag(base,LPSPI_RX_DATA_FLAG); /* Clear RDF flag */
return DataValue;
}微信图片_20190212201011.jpg

See the attached code.

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liulei1
Contributor II

Thanks, the problem has been solved, I disable the PCS function, the way the CS pin passes GPIO。But I don't know if I have a problem with this operation.

PCC->PCCn[PCC_PORTB_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
PORTB->PCR[2]|=PORT_PCR_MUX(3); /* Port B2: MUX = ALT3, LPSPI1_SCK */
PORTB->PCR[3]|=PORT_PCR_MUX(3); /* Port B3: MUX = ALT3, LPSPI1_SIN */
PORTB->PCR[4]|=PORT_PCR_MUX(3); /* Port B4: MUX = ALT3, LPSPI1_SOUT */

PORTB->PCR[5]|=PORT_PCR_MUX(1); /* Port B5: MUX = ALT1, LPSPI1_PCS1 */
PTB->PDDR |= (1<<5);
PTB->PSOR |= (1<<5);

PCC->PCCn[PCC_LPSPI0_INDEX] &= ~PCC_PCCn_CGC_MASK; /* Disable clocks to modify PCS ( default) */
PCC->PCCn[PCC_LPSPI0_INDEX] = PCC_PCCn_PR_MASK
| PCC_PCCn_PCS(2) /* Enable PCS=SIRC (8 MHz func'l clock) */
| PCC_PCCn_CGC_MASK; /* Enable clock for LPSPI regs */


LPSPI_Disable(LPSPI0); /* Disable module for configuration */
LPSPI_SetIntMode(LPSPI0,LPSPI_ALL_STATUS,false); /* Interrupts not used */
LPSPI_SetTxDmaCmd(LPSPI0,false); /* DMA not used */
LPSPI_SetRxDmaCmd(LPSPI0,false); /* DMA not used */
LPSPI_SetMasterSlaveMode(LPSPI0, LPSPI_MASTER); /* Set for master mode */
LPSPI_SetPinConfigMode(LPSPI0, LPSPI_SDI_IN_SDO_OUT, LPSPI_DATA_OUT_RETAINED, false);
LPSPI_ClearStatusFlag(LPSPI0,LPSPI_ALL_STATUS);

LPSPI_SetBaudRateDivisor(LPSPI0,2); /* SCKDIV=8: SCK divider =2+2 = 4 (1 usec: 500000 baud rate) */
LPSPI_SetDelay(LPSPI0, LPSPI_SCK_TO_PCS, 4); /* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */
LPSPI_SetDelay(LPSPI0, LPSPI_PCS_TO_SCK,9); /* PCSSCK=9: PCS to SCK delay = 9+1 = 10 (1 usec) */
LPSPI_SetDelay(LPSPI0, LPSPI_BETWEEN_TRANSFER, 8);/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */
//LPSPI_SetPcsPolarityMode(LPSPI0,LPSPI_PCS1 ,LPSPI_ACTIVE_LOW);
LPSPI_SetSamplingPoint(LPSPI0, false);

LPSPI_SetRxWatermarks(LPSPI0,0); /* RXWATER=0: Rx flags set when Rx FIFO >0 */
LPSPI_SetTxWatermarks(LPSPI0,3); /* TXWATER=3: Tx flags set when Tx FIFO <= 3 */
LPSPI_SetTxCommandReg(LPSPI0,&Spi_TxCmdCfgSet);

LPSPI_Enable(LPSPI0); /* Enable module for operation */
/* DBGEN=1: module enabled in debug mode */
/* DOZEN=0: module enabled in Doze mode */
/* RST=0: Master logic not reset */
/* MEN=1: Module is enabled */

/* Select sFLASH: Chip Select pin low */
#define OL_SDK_sFLASH_CS_LOW() OLA_SDK_GPIO_ResetBits(PTB,PIN5_IDX)
/* Deselect sFLASH: Chip Select pin high */
#define OL_SDK_sFLASH_CS_HIGH() OLA_SDK_GPIO_SetBits(PTB,PIN5_IDX)

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thomsonzhou
Contributor III

Hi,

   Do you know how to configure SPI corresponding registers before you use SPI.

You need to check the manual how to configure the register bits exactly.

   BTW, use your multimeter to check the power circuit part and other important circuit parts to check if the oscillator works normally or not.

Thomson

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razva_tilimpea
NXP Employee
NXP Employee

Hi Lei,

I tried to take a look over your project but is hard to check it because you mix register write, public API and hardware abstraction layer which shouldn't be used by application layer.

 

I think the problem is on your pins configuration. I don't see where pins direction is configured in OL_SDK_LPSPI_Init, there is configured just mux for your signals.

Best regards,

Razvan

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