s32K144 can bus off

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s32K144 can bus off

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shingozhou
Contributor III

Hi,

I have some questions about can bus-off.
1. MCU will reset CAN peripheral automatically after enter into bus-off status? Could change it to manual control and call the     lib funtion FLEXCAN_DRV_Init() again?

2. After reset CAN peripheral automatically because of bus-off status, Which register can be set or read to recognise the        CAN bus status now?

3. In order to detect CAN bus status after MCU have entered into CAN bus-off status, how to configure the key    regesters(disable automatic recovering from bus off)?

 Now, I configure the CTRL1[BUFFREC] = 1(disable automatic recovering from bus off), enable bus off interrupt. while       MCU detected CAN bus-off status, It generate an Interrupt and enter into ISR void CAN0_ORed_IRQHandler(void), in       this function, clear the interrupt flag(CAN0->ESR1[BOFFINT]).But it could not be generated bus-off Interrupt again. To       generate bus-off interrupt again, what should I do?

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AnaAldescu
NXP Employee
NXP Employee

Hello,

The FlexCAN driver does not offer an API for disabling automatic bus off recovery. Automatic recovering from Bus Off state occurs according to the CAN Specification 2.0B.

In order to check the current state of the module, you must call the FLEXCAN_DRV_GetErrorStatus (returns the value of the ESR1 register). Unfortunately, this function will only be available in the next SDK release.

Automatic bus off recovery can be disabled by setting the CTRL1[BOFFREC] bit. If the bit is asserted, automatic recovering from Bus Off is disabled and the module remains in Bus Off state until the bit is negated by the user. If the
negation occurs before 128 sequences of 11 recessive bits are detected on the CAN bus, then Bus Off
recovery happens as if the BOFFREC bit had never been asserted. If the negation occurs after 128
sequences of 11 recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for 11
recessive bits before joining the bus. After negation, the BOFFREC bit can be re-asserted again during
Bus Off, but it will be effective only the next time the module enters Bus Off. If BOFFREC was negated
when the module entered Bus Off, asserting it during Bus Off will not be effective for the current Bus Off
recovery.

The ESR1[BOFFINT] bit is set when FlexCAN enters ‘Bus Off’ state. If CTRL1[BOFFMSK] is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.

Best regards,

Ana

7,162 Views
shingozhou
Contributor III

hello, Ana:

I debug the program using S32K14x EAR SDK v0.8.4 release in S32DS v2.0. connected the two wires "CAN_H" and "CAN_L" short, an interrupt is generated, MCU enter into ISR(interrupr service routine) and the function FLEXCAN_IRQHandler( ) be executed,  the CAN0->ESR1 is read and clear all error interrupt in this function FLEXCAN_IRQHandler( ). that's to say, I can read the ESR1 register directly anytime. Is the analysis correct?

Now the probrem is ,the CAN0 can be recovery from bus off staus, by rebooting the CAN peripheral? Note: set automatic recover from bus off status disabled.

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

if you have automatic recovering disabled (CTRL1[BUFFREC] = 1), the module stays in Bus Off until this bit is negated by user. So after you get Bus off interrupt you should clear BUFFREC bit, then this bit can be set again if manual recovering from Bus off is required.

BR, Petr 

7,163 Views
charles_wangw
Contributor III

Hi Thank you very much

It works now. But I find one thing which make me a little confused.

1. When I connect CANH & CANL, Bus off interrupt will be create

2. When I connect CANH & Battery Low, Bus off interrupt will be create

3. When I connect CANH & Battery High, Bus off interrupt will not be create

4. When I connect CANL & Battery Low, Bus off interrupt will not be create

5. When I connect CANL & Battery High,  Bus off interrupt will be create

While I want all the 5 case above can create interrupt. Is my register configuration not correct or the two case should not create interrupt?

Thank you very much.

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7,165 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

yes, for those 2 cases (CANH shorted to Vbat, CANL shorted to GND) the transmission is still working, only there will be distorted voltage levels on the bus. Thus the bus off state is not entered.

BR, Petr 

7,164 Views
charles_wangw
Contributor III

Hello Petr

Our Customer(EB) heard NXP side already create an ticket about this suspend ?(MCAL-22129). If this information is correct? If the ticket is true could please share the release note about this? We side never seen this before. We need EB side to update this to fix the issue(We can not go to freeze mode while we don't suspend the interrupt during update the register).

Thank you very much.

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charles_wangw
Contributor III

Hello Petr

I still have a question about Bus off Interrupt. I see from some place(I can not find it again). When we try to set the register to enter in freeze mode. We need to suspend the interrupt? Because during my test if the interrupt never be suspend, I will never get the bus off interrupt. Could you please share some information or document about this? Thank you very much.

Charles

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charles_wangw
Contributor III

Thanks

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charles_wangw
Contributor III

Hello Shingo

I have the same issue with you. When I connect CANH & CANL and never move away. It seems I can go inside the interrupt one time. I have no idea if we can go to the interrupt again with this phenomenon. Have you solved your issue?

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