Hi,
That delay is caused by the high clock frequency used in your application. This behavior is expected because the IRQ handlers doesn't have enough time to re-fill the buffers.
You can easily convert your example to work with DMA:
1. In DMA component add 2 channels. Let's say that we use channel 0 and channel 1
2. Configure the LPSPI component to work with channels 0 an 1.
3. Configure DMA in your application:
EDMA_DRV_Init(&dmaController1_State, &dmaController1_InitConfig0, edmaChnStateArray, edmaChnConfigArray, EDMA_CONFIGURED_CHANNELS_COUNT);
If you have problems on receiving side for master device please set SAMPLE bit from CFGR1. This issue will be fixed on our next release.
Best regards,
Razvan
