Why is CS pulled high before LPSPI has finished transmitting?

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 
已解决

Why is CS pulled high before LPSPI has finished transmitting?

跳至解决方案
4,638 次查看
kalvin
Contributor I

void SPI_Init(LPSPI_Type *instance,SpiSpeedType Speed)
{
instance->IER = 0x00000000; /* Interrupts not used */
instance->DER = 0x00000000; /* DMA not used */
instance->CFGR0 = 0x00000000; /* Defaults: */
/* RDM0=0: rec'd data to FIFO as normal */
/* CIRFIFO=0; Circular FIFO is disabled */
/* HRSEL, HRPOL, HREN=0: Host request disabled */
instance->CFGR1 = LPSPI_CFGR1_MASTER(1); /* Configurations: master mode */
/* PCSCFG=0: PCS[3:2] are enabled */
/* OUTCFG=0: Output data retains last value when CS negated */
/* PINCFG=0: SIN is input, SOUT is output */
/* MATCFG=0: Match disabled */
/* PCSPOL=0: PCS is active low */
/* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */
/* AUTOPCS=0: does not apply for master mode */
/* SAMPLE=0: input data sampled on SCK edge */
/* MASTER=1: Master mode */

instance->TCR |= LPSPI_TCR_PRESCALE(SpiSpeed.prescale)| /* PRESCALE=2: Functional clock divided by 40M/2 = 20M */
LPSPI_TCR_PCS(2) |
LPSPI_TCR_FRAMESZ(7); /* FRAMESZ=7: # bits in frame = 7+1=8 */

instance->CCR |= LPSPI_CCR_SCKDIV(SpiSpeed.sckdiv) | /* 20/(8+2) = 2M */
LPSPI_CCR_DBT(8) |
LPSPI_CCR_SCKPCS(4) |
LPSPI_CCR_PCSSCK(4);

instance->FCR = LPSPI_FCR_TXWATER(3); /* RXWATER=0: Rx flags set when Rx FIFO >0 */
/* TXWATER=3: Tx flags set when Tx FIFO <= 3 */
instance->CR = LPSPI_CR_MEN_MASK
|LPSPI_CR_DBGEN_MASK; /* Enable module for operation */
/* DBGEN=1: module enabled in debug mode */
/* DOZEN=0: module enabled in Doze mode */
/* RST=0: Master logic not reset */
/* MEN=1: Module is enabled */
}
uint8_t LPSPI_ReadWriteByte(LPSPI_Type *instance,uint8_t byte)
{
uint8_t recieve = 0;

while((instance->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
/* Wait for Tx FIFO available */
instance->TDR = byte; /* Transmit data */
instance->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */

while((instance->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
/* Wait at least one RxFIFO entry */
recieve= instance->RDR; /* Read received data */
instance->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */

return recieve; /* Return received data */
}

标记 (1)
0 项奖励
回复
1 解答
4,611 次查看
davidtosenovjan
NXP TechSupport
NXP TechSupport

It is given by following bits in Transmit Command Register (TCR):

davidtosenovjan_0-1663674698393.png

davidtosenovjan_1-1663674763269.png

 

 

在原帖中查看解决方案

0 项奖励
回复
8 回复数
4,612 次查看
davidtosenovjan
NXP TechSupport
NXP TechSupport

It is given by following bits in Transmit Command Register (TCR):

davidtosenovjan_0-1663674698393.png

davidtosenovjan_1-1663674763269.png

 

 

0 项奖励
回复
4,607 次查看
kalvin
Contributor I

 @davidtosenovjan thanks for your answer,but why there are three bytes before each byte is 0x00, please see the picture in the attachment .

0 项奖励
回复
4,589 次查看
davidtosenovjan
NXP TechSupport
NXP TechSupport

Why you are transmitting per four bytes when the function seems to be written per byte? Which data you are transmitting, it is not apparent from your code snippet.

0 项奖励
回复
4,563 次查看
kalvin
Contributor I

 @davidtosenovjan  The null byte problem has been solved, but I still have a question to ask, why does CS keep low level after TCD CONC is enabled? Please see the attached picture .

0 项奖励
回复
4,551 次查看
davidtosenovjan
NXP TechSupport
NXP TechSupport

Here you may read description to understand how to set CONT/CONTC bits:

https://community.nxp.com/t5/S32K/S32K14x-Command-Word-in-LPSPI/td-p/1040779

 

0 项奖励
回复
4,500 次查看
kalvin
Contributor I

Thanks @davidtosenovjan  my problem has been solved !

0 项奖励
回复
4,586 次查看
kalvin
Contributor I

transmit buffer is :

spi_buffer_t master_buffer =
{
.tx = {0xA,0xB,0xC,0xD,0xE,0xF,0x9,0x8,0x7,0x6,0x5,0x4,0x3,0x2,0x1,0xAA},
.rx = {0}
};

0 项奖励
回复
4,585 次查看
kalvin
Contributor I
 
0 项奖励
回复