Some ADC channel reading 0 in S32K146

Showing results for 
Search instead for 
Did you mean: 

Some ADC channel reading 0 in S32K146

Contributor I

Inputs considered are on SE0, SE1 and SE5 on ADC0. Back to back triggering has been enabled. If SE5 is disabled, correct values are obtained on the SE0 and SE1 channels. When SE5 input is enabled, all the values (var1, var & var3) show up as 0.

Any help?

PDB0->MOD = 1200;
PDB0->IDLY =1200;

PDB0->CH[0].C1 = (PDB_C1_BB(0x02)
| PDB_C1_TOS(0x01)
| PDB_C1_EN(0x03));

ADC_DRV_ConfigChan(INST_ADCONV1, ADC_INPUTCHAN_EXT0, &adConv1_ChnConfig0);
ADC_DRV_ConfigChan(INST_ADCONV1, ADC_INPUTCHAN_EXT1, &adConv1_ChnConfig1);

ADC_DRV_ConfigChan(INST_ADCONV1, ADC_INPUTCHAN_EXT5, &adConv1_ChnConfig2);

ADC0->SC1[0] = ADC_SC1_ADCH(0); // SC1A[ADCH]
ADC0->SC1[1] = ADC_SC1_ADCH(1); // SC1B[ADCH]
ADC0->SC1[2] = ADC_SC1_ADCH(5); // SC1F[ADCH]

var1 = ADC0->R[0]; 
var2 = ADC0->R[1];
var3 = ADC0->R[5];

0 Kudos
1 Reply

NXP TechSupport
NXP TechSupport


the setting does not look right for 3 channels conversion in back-to-back mode. You should have 

PDB0->CH[0].C1 = (PDB_C1_BB(0x06) | PDB_C1_TOS(0x01) | PDB_C1_EN(0x07)); 

Channel delay 0 register should be configured too, or simply clear TOS if delay of first sample is not needed.

Also you should read result from R0, R1, R2 registers

var3 = ADC0->R[2];

BR, Petr

0 Kudos