S32K322 STM0 can not work when StmFreezeEnable is set in GPT

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S32K322 STM0 can not work when StmFreezeEnable is set in GPT

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KidhRobin
Contributor I

hello,

 

I'm trying to config a STM0 timer with S32K322 ,

when I set StmFreezeEnable true, the STM0's CNT is always 0,do not change .

KidhRobin_0-1702365445819.png

 

when I set StmFreezeEnable false ,the STM0's CNT can update;

KidhRobin_1-1702365646533.png

 

I compare the two setting's code, the difference just this

KidhRobin_2-1702365709562.png

 

 

can some help me to fix this issue? Did I miss something?

Thank you 

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @KidhRobin,

The S32K322 has CM7_0 and CM7_1 decoupled.

Are both cores out of debug mode?

Have you tried with DCMRWD8[10] = 1, (STM_0 remains functional and unimpacted when the Cortex-M7_1 core enters Debug mode)?

 

Regards,

Daniel

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello @KidhRobin,

It is spected that the STM stops its operation in Debug mode when FRZ = 1.

danielmartynek_0-1702376294320.png

By default, all the STM_n timers stop when any of the cores enters the debug mode.

This can be changed in these registers:

DCMRWD6 - DCMRWD9

For example:

DCMRWD6[10]

danielmartynek_1-1702376388282.png

DCMRWD8[11]

danielmartynek_2-1702376463501.png

 

Regards,

Daniel

 

 

 

 

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KidhRobin
Contributor I

hi ,@danielmartyneak

Thanks for your replay.

Currently, I am using S32K322, and the related driver code is configured using EB, with the debugger being PE.

My understanding is that when configuring the StmFreezeEnable to true (below picture)in the GPT STM modules, entering a breakpoint during debugging should pause the STM CNT counter.

KidhRobin_2-1702514551125.png

When running, the STM CNT should count normally.

Is my understanding correct?

 
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danielmartynek
NXP TechSupport
NXP TechSupport

Yes, that is correct.

 

BR, Daniel

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KidhRobin
Contributor I

Thank you for reply.

What the issue is  when I set the StmFreezeEnable to true , but the STM0 Cnt always 0, do not update anymore, 

can you tell me how to solved this issue?

I'm using PE and S32DS V3.5 now.

Thank you

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @KidhRobin,

The S32K322 has CM7_0 and CM7_1 decoupled.

Are both cores out of debug mode?

Have you tried with DCMRWD8[10] = 1, (STM_0 remains functional and unimpacted when the Cortex-M7_1 core enters Debug mode)?

 

Regards,

Daniel

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531 Views
KidhRobin
Contributor I

hi, @danielmartynek 

thank you for replay, it can works now by add the code,

KidhRobin_0-1702885955194.png

 

but  can I config in the S32DS Configure tools ?

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