S32K32 and K3x family communication and interactions between different cores

[Simone9]

Good morning,

I wanted to get some information about the S32K32 microcontrollers or in general the K3 family with multiple cores.

In particular, I wanted to know the following information:
- How the two M7 cores can exchange information and data
- If one core starts before the other and if the core that starts first can decide whether to start the other one or not
- Are there exclusive peripherals per core or just be careful that one core does not disturb the peripheral of managed by the other core
- Can a core be deprived of access to a peripheral?
- Should the setting, during initialization, of the microcontroller ports be done identically by the two cores?

I ask these questions because I am having difficulty finding this information.

Thank you very much for your support

[lukaszadrapa · Accepted solution]

Hi @Simone9 

- How the two M7 cores can exchange information and data
* Both cores can access whole memory map, so data can be exchanged via shared RAM segment. Software interrupt can be used to inform other core that new data are prepared.
An option is to use "Inter-Platform Communication Framework" which is included in S32K3 Standard Software package:
https://www.nxp.com/webapp/swlicensing/sso/downloadSoftware.sp?catid=SW32K3-STDSW-D

- If one core starts before the other and if the core that starts first can decide whether to start the other one or not
* It is possible to define which cores will start automtically after reset in Boot Configuration Word in IVT. A core which is not started in this way can be started by software like this:
MC_ME->PRTN0_CORE1_ADDR = (uint32_t)(vtor);
MC_ME->PRTN0_CORE1_PCONF = MC_ME_PRTN0_CORE1_PCONF_CCE_MASK;
MC_ME->PRTN0_CORE1_PUPD = MC_ME_PRTN0_CORE1_PUPD_CCUPD_MASK;
MC_ME->CTL_KEY = MC_ME_CTL_KEY_KEY( 0x5AF0);
MC_ME->CTL_KEY = MC_ME_CTL_KEY_KEY(~0x5AF0);

- Are there exclusive peripherals per core or just be careful that one core does not disturb the peripheral of managed by the other core
* It is possible to use Extended Resource Domain Controller (XRDC). See please the reference manual for more details.

- Can a core be deprived of access to a peripheral?
* Yes, see please XRDC.

- Should the setting, during initialization, of the microcontroller ports be done identically by the two cores?
* The cores share the same resources (peripherals, memories...). If one core already initialized something, it obviously does not need to be configured again by second core.

Regards,
Lukas