Hi @LijieDu,
The eDMA has its own arbitration control (CR[RECA]).
And there is arbitration on the crossbar switch too:
have you set CBRR = 1.
BR, Daniel
I have set CBRR to 1, and it has no improvement.
The left side of the figure shows the measured values when the DMA destination address is set to the peripheral register.
The right side of the figure shows the measured values when the DMA destination address is set to the RAM space.
Only difference is destination address.
SysClk is 48MHz.
DMA trigger frequency is about 30khz（trigger DMA function every 33us）, duration is about 30ms when enable DMA transfer function.
The description of the image:
Picture above shows: Measured values when the DMA destination address is set to the peripheral register and DMA is triggered in real time. We can see that the values get from ADC is unstable.
Picture above shows: Measured values when the DMA destination address is set to the RAM space and DMA is triggered in real time. We can see that the values get from ADC is stable.
I see, thank you.
Have you tried using a different pin for the PWM output?
BR, Daniel
Hi @LijieDu,
There can be two issues, and we have already touched on that.
- Arbitration
The DMA concept cannot be exactly deterministic, becasue the Core and the eDMA access the same resources through the crossbar switch and the peripheral bridge.
Before the GPIO pins are switched to High-Z, the ADC sampling already starts (1) to removed any remaining charge in the ADC sample and hold capacitor.
1. ADC is triggered
2. GPIO in HIGH-Z
X. Sample ends (pin disconnected from ADC), conversion starts
3. Converion ends
If the ADC is triggered (1) with some delay due to arbitration, the sample phase starts and ends in different poinst, and this leads to incorrect measurement.
Can you try with a longer Sample time?
Do you use DMA to trigger the ADC conversions too?
- Crosstalk, EMC
The high freq. PWM signal should not be at a pin adjacent to the touch sense pins (and traces).
Regards,
Daniel
