S32K312 send uart data fail

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S32K312 send uart data fail

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139 次查看
jhuang1
Contributor I

Hello, I want to send data via uart + dma, and the program works fine on RTD 2.0.3. But when I transport it to RTD 4.0.0, the uart can only recieve data successfully, it sent "00" always at the trasmitting side. The test program I uploaded recieves data and transmit them out, it can recieve right fix data like 0~16, but transmit 16 zeros. please help me to check the program, thanks.

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52 次查看
Robin_Shen
NXP TechSupport
NXP TechSupport

If it works properly after delete D_CACHE_ENABLE in Defined symbols, then it should be related to data cache.

D_CACHE_ENABLE DMA UART.png

Try putting the buffer in a non cacheable memory section:

#define UART_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
#include "Uart_MemMap.h"
__attribute__(( aligned(32) )) uint8 rxdata[256u];

#define UART_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
#include "Uart_MemMap.h"

 

Are UartSend and UartReceive your own APIs? Do S32K3 RTD APIs such as Uart_AsyncSend and Uart_AsyncReceive work properly?

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112 次查看
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi 

Please place the buffer in a non cacheable memory section.

In the DMA transfer mode, DMA transfers may have cache coherency problems. To avoid possible coherency issues when D-CACHE is enabled, the user shall ensure that the buffers used as TCD source and destination are allocated in the NON-CACHEABLE area (by means of Uart_Memmap). Otherwise, the Uart driver has some dependencies. User must to put all variables, which were used for transmitter and receiver, in the NON CACHEABLE memory section in the RAM zone by the definition UART_START_SEC_VAR_<INIT_POLICY>_<ALIGNMENT>_NO_CACHEABLE and UART_STOP_SEC_VAR_<INIT_POLICY>_<ALIGNMENT>_NO_CACHEABLE.

DMA transfer mode buffer D-CACHE enabled NON-CACHEABLE.png


Best Regards,
Robin
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108 次查看
jhuang1
Contributor I

Hi, thank you for reply, I tried to disable the whole dcache before uart test, but the problem hadn't been solved.

/*start uart dma rx*/
UartRxDmaStart(6U, UART_CONFIG.RxDMAChannel);
 
Mcl_CacheDisable(MCL_CACHE_LMEM,MCL_CACHE_ALL_BUS);
Mcl_CacheDisable(MCL_CACHE_CORE,MCL_CACHE_ALL_BUS);
 
    /**************************************************/
    /* Main example loop                              */
    /**************************************************/
    while(1)
    {
    //UartSend(6u,UART_CONFIG.TxDMAChannel,rxdata, 10);
    UartReceive(6u,UART_CONFIG.RxDMAChannel,rxdata,&rxlen,100U);
if(rxlen > 0)
{
 
UartSend(6u,UART_CONFIG.TxDMAChannel,rxdata, rxlen);
 
 
}
 
    }
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53 次查看
Robin_Shen
NXP TechSupport
NXP TechSupport

If it works properly after delete D_CACHE_ENABLE in Defined symbols, then it should be related to data cache.

D_CACHE_ENABLE DMA UART.png

Try putting the buffer in a non cacheable memory section:

#define UART_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
#include "Uart_MemMap.h"
__attribute__(( aligned(32) )) uint8 rxdata[256u];

#define UART_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
#include "Uart_MemMap.h"

 

Are UartSend and UartReceive your own APIs? Do S32K3 RTD APIs such as Uart_AsyncSend and Uart_AsyncReceive work properly?

0 项奖励