Hello
I saw in the S32K3xx Low Power Management.pdf that there is such a description in the [6.3. VLSR mode entry] chapter [FIRC must be divided by 16 to provides a 3 MHz clock source for the core, the bus, the peripheral clocks and flash memory access mode (750 KHz).].
I use the DS tool to configure a clock tree different from RUN Mode, which uses FIRC as the clock source, but the FIRC clock cannot be divided by 16 to assign to CORE_CLK, and the value of clock division is at most 8.
How to divide FIRC into 16 when entering StangBy?
BestRegards
