When the AIPS-PLAT-CLC clock is at 60M, the flash is normal.
When 40M, FALSH will stop in Wait until interlock write finishes
Do you know what causes the impact?
AIPS_SLOW_CLK must be half of AIPS_PLAT_CLK as it is required by all clocking options.
When the AIPS-PLAT-CLC clock is at 60M, the flash is normal.
When 40M, FALSH will stop in Wait until interlock write finishes
Do you know what causes the impact?
AIPS_SLOW_CLK must be half of AIPS_PLAT_CLK as it is required by all clocking options.
