S32K3 FLEXCAN LEGACY RX FIFO

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S32K3 FLEXCAN LEGACY RX FIFO

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288件の閲覧回数
Neo1096
Contributor I

In LEGACY RX FIFO mode using FLEXCAN, is there no storage depth for the hardware?
If you have a storage depth, such as the 16 Rx FIFO Filters I use here, which take up 10 mailboxes, you can add 16 filters. But I only have FlexCAN_Ip_RxFifo(INST_FLEXCAN_0,&Rxbuf) in the interrupt; This function can read FIFO values under CAN0. If my CAN interrupt priority is low, how can I read other frames stored in the FIFO? In addition, why do these 10 mailboxes also need to set masks?
I want to implement CAN frames CAN be saved in the mailbox, at a low CAN priority, or use a query to read CAN frames, and ensure that no frames are lost.
I see in the routine what seems to be a software-implemented FIFO, which is not what I want.
Or I might as well use the standard mail function and set up a few more mailboxes that match the ID that receives the most frequently.
Or do you use FIFO and open DMA?

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268件の閲覧回数
PetrS
NXP TechSupport
NXP TechSupport

Hi,

legacy RXFIFO can hold up to 6 messages without CPU intervention, if more messages comes it can be lost if RXFIFO is not read out in time. RTD driver is written in a way you need to call FlexCAN_Ip_RxFifo first, an interrupt is called once there is at least 1 message in the RXFIFO, driver reads single message from RXFIFO and user have to call FlexCAN_Ip_RxFifo again to enable interrupt again. Similar operation is done if DMA mode is selected, still FlexCAN_Ip_RxFifo must be called to get a data.
If 16 filter elements are selected, first 10 elements use first 10 individual mask acceptance registers to provide acceptance mask (assuming individual masking scheme is selected).
Beside RXFIFO you can use rest of available MBs for TX or RX functionality.

You can refer to below example ...
https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-CAN-Transmit-amp-Receive-Using-MB-a...

BR, Petr

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269件の閲覧回数
PetrS
NXP TechSupport
NXP TechSupport

Hi,

legacy RXFIFO can hold up to 6 messages without CPU intervention, if more messages comes it can be lost if RXFIFO is not read out in time. RTD driver is written in a way you need to call FlexCAN_Ip_RxFifo first, an interrupt is called once there is at least 1 message in the RXFIFO, driver reads single message from RXFIFO and user have to call FlexCAN_Ip_RxFifo again to enable interrupt again. Similar operation is done if DMA mode is selected, still FlexCAN_Ip_RxFifo must be called to get a data.
If 16 filter elements are selected, first 10 elements use first 10 individual mask acceptance registers to provide acceptance mask (assuming individual masking scheme is selected).
Beside RXFIFO you can use rest of available MBs for TX or RX functionality.

You can refer to below example ...
https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-CAN-Transmit-amp-Receive-Using-MB-a...

BR, Petr

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Neo1096
Contributor I
Thank you very much, you mentioned in your reply, written in a way that calls FlexCAN_Ip_RxFifo first, once there is at least 1 message in RXFIFO, the call breaks.
CAN I understand that I first call this function once during initialization, so if I have a message I will enter the interrupt, and if there are more than two messages, I will immediately enter the CAN interrupt again after reading the message for the first time and exiting the interrupt?
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200件の閲覧回数
PetrS
NXP TechSupport
NXP TechSupport

Hi,

for more messages, if you call FlexCAN_Ip_RxFifo again after entering interrupt, it will be called again, as RXFIFO contains message to be read.

BR, Petr

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184件の閲覧回数
Neo1096
Contributor I
If I receive a message through a FIFO mode interrupt, how do I know what filter value I set for the message? Can you search through the register? It's still just the software that walks through the filter values that I set.
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PetrS
NXP TechSupport
NXP TechSupport

Hi,

you can use CAN2_FIFO_Received_MB[x].id_hit, which is Identifier Acceptance Filter Hit Indicator.

BR, Petr

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