S32K1xx Power down and power on reset procedure

[siva280386]

We are working on S32K148 micro. As per the data sheet we see the POR will be detected when Vcc is <1.6V . Is there any problem if the Vcc is not dropping to 0V before we power on the micro with 3.3V Vcc, to detect a valid POR? Is there any rise time and fall time requirements for detecting power down and power on reset? Is there any specific application note available that details the procedure during the power down and power on reset of the micro? I could find only the details on specific operation power modes , but not the details on the power down and power on reset operation of the micro.

[Robin_Shen]

Hi

Please refer to the "2.2 MCU power supply ramp rate" of AN5426: Hardware Design Guidelines for S32K1xx – Application Note

Best Regards,
Robin
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[siva280386]

Hi Robin, 

Thanks for the details.

in datasheet Vdd_Off is showing min value as 0V. so, what might happen if the Vdd is dropped below 1.5V ( but not 0V) and ramped to 3.3V following the ramp timings. Does the  micro see a valid POR in all conditions ? or is it always supposed to be coming from 0V ? we had a scenario where our Vdd is not dropping to 0V in some cases , it was stuck at 0.5V. 

Also , any details on the power down and power on reset procedure internal to the micro boot up?

[Robin_Shen · Accepted solution]

Max VDD_OFF=0.1V so 0.5V is still violate the specification.
As the AN5426 mentioned: The outcome of violating the specification causes unexpected behavior, stuck operation or damage in the MCU.