S32K144 CAN1 MB0 and MB1 receive and transfer problem

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S32K144 CAN1 MB0 and MB1 receive and transfer problem

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Hal_9000
Contributor II
I use S32K144 CAN1, PORT PTE12 for RX and PTE13 for TX. I use MB0 for receiving and MB1 for transferring. Now I enable MB0 interrupt and disable MB1 interrupt in IMASK1 register,only enable receiving and transferring successfully interrupt by using INT_SYS_SetPriority(CAN1_ORed_0_15_MB_IRQn,2); and not enable other interrupt source.In interrupt Handler —— CAN1_ORed_0_15_MB_IRQHandler ,when I received frame,I clearing MB0 bit in IFLAG1 and sending a permanent TX frame to MB1.
 
Now i say my problem ,if I delete send function in CAN1_ORed_0_15_MB_IRQHandler ,everything will be ok,When I send a frame to board by using upper computer,I can successfully received a frame ,clear MB0 to IFLAG1 register and not continued enter in CAN1_ORed_0_15_MB_IRQHandler .But adding send function,when I received a RX frame ,the TX frame is sent and quit CAN1_ORed_0_15_MB_IRQHandler ,it will also continue entering in CAN1_ORed_0_15_MB_IRQHandler endlessly .When using PE debug ,I found MB0 in IFLAG1 register changed to 1,it can explain this phenomenon. But I had clean this bit by writing 1 to this bit .Why cause this?
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PetrS
NXP TechSupport
NXP TechSupport

Hi,

this could be caused if self-receive functionality is enabled (MCR[SRXDIS]=0) and if the RX MB is programmed with
an ID that matches the transmitted frame. So please check this and eventually set SRXDIS bit in Freeze mode.

BR, Petr

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1,470 次查看
PetrS
NXP TechSupport
NXP TechSupport

Hi,

this could be caused if self-receive functionality is enabled (MCR[SRXDIS]=0) and if the RX MB is programmed with
an ID that matches the transmitted frame. So please check this and eventually set SRXDIS bit in Freeze mode.

BR, Petr

1,469 次查看
Hal_9000
Contributor II

Thx for your reply!It does really work!

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