S32K142 Pflash Erase Fault

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S32K142 Pflash Erase Fault

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1069466534
Contributor II

"Hello, when performing UDS (Unified Diagnostic Services) flashing on a vehicle, we encountered an issue where the erase function reported an error, resulting in an unsuccessful flash write. Upon powering down the ECU (Electronic Control Unit) and then re-energizing it, and attempting to trigger the flash again, the error persisted, preventing the ECU from completing the flash write process. What could be the potential reasons leading to this problem?"

START_FUNCTION_DEFINITION_RAMSECTION
static status_t FLASH_DRV_CommandSequence(const flash_ssd_config_t * pSSDConfig)
{
status_t ret = STATUS_SUCCESS; /* Return code variable */

/* Clear CCIF to launch command */
FTFx_FSTAT |= FTFx_FSTAT_CCIF_MASK;

while (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
{
/* Wait till CCIF bit is set
* Serve callback function as often as possible
*/
if (NULL_CALLBACK != pSSDConfig->CallBack)
{
/* Temporarily disable compiler's check for ROM access call from within a ram function.
* The use of a function pointer type makes this check irrelevant.
* Nevertheless, it is imperative that the user-provided callback be defined in RAMSECTION */
DISABLE_CHECK_RAMSECTION_FUNCTION_CALL
(pSSDConfig->CallBack)();
ENABLE_CHECK_RAMSECTION_FUNCTION_CALL
}
}

/* Check if an error is occurred */
if ((FTFx_FSTAT & (FTFx_FSTAT_MGSTAT0_MASK | FTFx_FSTAT_FPVIOL_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_RDCOLERR_MASK)) != 0U)
{
ret = STATUS_ERROR;  
}

return ret;
}
END_FUNCTION_DEFINITION_RAMSECTION

"During the debugging process, we discovered that the value of the FSTAT register is 0x81, with the MGSTAT0 bit set to 1. We are interested in understanding what circumstances could lead to this bit being set to 1. What steps can we take to resolve this issue? Should we consider re-flashing the unit using a programmer?"

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @1069466534,

The Erase Flash Sector command verifies the sector is properly erased, if not MGSTAT0 is set.

Lauch the command again to erase the sector again.

Do you mask interrupts before the command is launched?

 

Regards,

Daniel

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833 Views
1069466534
Contributor II

I have set the interrupt disable, and I am currently suspecting that the possible reason is excessive erase-write cycles on a Sector of the PFLASH. What is the minimum endurance count for erase-write operations on PFLASH?

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817 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hello @1069466534,

The min. endurance is 1000 cycles.

danielmartynek_0-1715084928060.png

 

 

815 Views
1069466534
Contributor II

Thank you for your question. If the FLASH memory is damaged during erase, can a full erase operation cause the chip to become locked or unusable?

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danielmartynek
NXP TechSupport
NXP TechSupport

Yes, the Flash Configuration Field might be in an undefined state, which can cause the MCU to be locked permanently.

Also, keep in mind that when CSEc keys are allocated, the Mass erase operation is not possible.

AN12130 Production Flash Programming Best Practices for S32K1xx MCUs

https://www.nxp.com/docs/en/application-note/AN12130.pdf

3.2.5.2 Mass erase and CSEc considerations

5 Common problems

 

BR, Daniel

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788 Views
1069466534
Contributor II

Thanks. Daniel

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831 Views
1069466534
Contributor II

1069466534_0-1715046428729.png

When a faulty component undergoes a full erase process through a PE burner, the chip becomes locked and cannot be unlocked. Through inspection of the strategy reset pin, it is found that the reset pin periodically pulls low for 118 microseconds. Based on the above, can you provide possible reasons?

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