Hello @danielmartynek,
I want to use S32K148 LPSPI module to communicate with a RF module. I don't want to use SDK or RTD drivers. The module interface is based on 3-wire SPI (half duplex). The communication method is that first I send a byte(register address) on the data line and then the slave module puts a byte(register read data) on the SDIO (data line) in response.
The image below is a part of the slave module datasheet. As shown in the picture, the manufacturer recommends that the MCU changes the state of its data line to the input before the last falling edge of the clock, so that it does not overlap with the time, slave turns to output state (which occurs after the mentioned falling edge).
As I have specified in the image above, I guess that the MCU changes the state of the SDIO line to input, after the recommended edge, and there is an interval of time in which both sides are at output state.
I want to use the register level routine, introduced in this topic:
https://community.nxp.com/t5/S32K/S32K-3-Wire-SPI-Drivers/td-p/1342666
What should I do to make sure that the warned contention will not occur on the SDIO line?
Thanks a lot
Hi @Jembed,
Please find my test project attached.
It sends one 16b frame (RXMSK = 1) and reads one 16bit frame (TXMSK = 1) in continous mode (CPHA = 0, CPOL = 0, PINCFG = 2, OUTCFG = 1 ).
SOUT (PTB16) is connected to a voltage divider, SOUT = 2.7V in High-Z mode.
As you can see, the SOUT is released (High-Z) at the last falling edge of SCK.
Regards,
Daniel
Hi @Jembed,
Please find my test project attached.
It sends one 16b frame (RXMSK = 1) and reads one 16bit frame (TXMSK = 1) in continous mode (CPHA = 0, CPOL = 0, PINCFG = 2, OUTCFG = 1 ).
SOUT (PTB16) is connected to a voltage divider, SOUT = 2.7V in High-Z mode.
As you can see, the SOUT is released (High-Z) at the last falling edge of SCK.
Regards,
Daniel
