LPUART TX DMA issue S32K1xx

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LPUART TX DMA issue S32K1xx

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chandan_uv
Contributor III

I am using S32K146 and using UART TX and RX with DMA. Its working fine most of time but sometime unable to tx as lpuart0_state.isTxBusy doesn't reset to false. As this is rarely occurring, I am unable to reproduce it for debugging. Below are the configuration for UART. Please let me know how to debug it. 

- lpuart0_state. transmitStatus is busy

- edma_chn_state_t.status is channel normal.

Below are the LPUART0 and DMA register data during the issue

chandan_uv_0-1722599758530.png

chandan_uv_1-1722599776222.png

 

 

chandan_uv_2-1722599782061.png

 

 

void init_uart(void){
	  status_t ret = STATUS_SUCCESS;

    lpuart_user_config_t lpuart1_cfg;
	
	  edma_init_iot_comm();

    lpuart1_cfg.transferType = LPUART_USING_DMA;
    lpuart1_cfg.baudRate = 1000000; 
    lpuart1_cfg.parityMode = LPUART_PARITY_DISABLED;
    lpuart1_cfg.stopBitCount = LPUART_ONE_STOP_BIT;
    lpuart1_cfg.bitCountPerChar = LPUART_8_BITS_PER_CHAR;
    lpuart1_cfg.rxDMAChannel = EDMA_CHN1_NUMBER;
    lpuart1_cfg.txDMAChannel = EDMA_CHN0_NUMBER;

    ret = LPUART_DRV_Init(UART_COM_4G, &lpuart0_state, &lpuart1_cfg);

    DEV_ASSERT(ret == STATUS_SUCCESS);
	
	  // setLpuartHardFlowCtrl();

    LPUART_DRV_InstallTxCallback(UART_COM_4G, lpuart_tx_callback_t, NULL);

    LPUART_DRV_InstallRxCallback(UART_COM_4G, lpuart_rx_callback_t, NULL);
	
	  LPUART_DRV_ReceiveData(UART_COM_4G, iot_rx_struct.data, MAX_RX_IOT_COMM_BUFFER);
		
		IOT_COMM_UART_FLOW_START_RX;
		
}

 

static status_t edma_init_iot_comm(void){
    status_t ret = STATUS_SUCCESS;
    
    edma_chn_state_t *const edma_channel_states[] = {
        &dma_ctrl_chn0_state,
        &dma_ctrl_chn1_state
    };

    edma_channel_config_t dm_chn0_cfg = {
        .channelPriority = EDMA_CHN_PRIORITY_1,
        .virtChnConfig = EDMA_CHN0_NUMBER,
        .source = EDMA_REQ_LPUART0_TX,
        .callback = NULL,
        .callbackParam = NULL,
        .enableTrigger = false
    };
    
    edma_channel_config_t dm_chn1_cfg = {
        .channelPriority = EDMA_CHN_PRIORITY_0,
        .virtChnConfig = EDMA_CHN1_NUMBER,
        .source = EDMA_REQ_LPUART0_RX,
        .callback = edma_RX_callback, //NULL,
        .callbackParam = NULL,
        .enableTrigger = false
    };
    
    const edma_channel_config_t *const edma_chn_cfg_arr[] = {
        &dm_chn0_cfg,
        &dm_chn1_cfg
    };

    edma_user_config_t dma_ctrl_init_cfg = {
        .chnArbitration = EDMA_ARBITRATION_FIXED_PRIORITY,
        .haltOnError = false
    };
    
    ret = EDMA_DRV_Init(&dma_ctrl_state, &dma_ctrl_init_cfg, edma_channel_states, edma_chn_cfg_arr, EDMA_CONFIGURED_CHANNELS_COUNT);  
    
		DEV_ASSERT(ret == STATUS_SUCCESS);
		
    return ret;
}

 

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136 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@chandan_uv

We are currently overloaded and response times are slow, thank you for your understanding.

Can you provide a demo so we can reproduce your issue?

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203 Views
chandan_uv
Contributor III

I debugged more during the issue

- LPUART DMA TX request bit is still set

chandan_uv_0-1722859500498.png

- In DMA, DMA request signal bit is 0

chandan_uv_1-1722859560919.png

 

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