hi everyone:
I find when i use S32K146 to communicate with slave,the I2C frequency will reduction if i connect more than 5 slaves. My question is :
1、Is there a quantitative formula for the relationship between load and frequency?
2、The rising edge time exceeds which critical value will affect my minimum high level time?
Hi,
1. The Timing Parameters are explained in the RM rev.12.1 Section 52.3.2.4.
SCL/SDA_RISETIME is given by the resistance of the pull-ups and the capacitance of the bus.
So you can adjust the parameters (make sure it follows the Table 52-8. LPI2C Timing Parameter Restrictions) or use stronger pull-ups.
2. Yes, the HIGH period of the SCL clock depends on the SCL_LATENCY as well.
Regards,
Daniel