Hi NXP team,
In RUN mode we have used PE clock as oscillator clock (8MHz) and module clock as SYS_CLOCK (80MHz). Since CAN can only support SIRC clock (8MHz) in VLPR, this may change the FLEXCAN bit rate (kbps) after switching from RUN to VLPR. Could you please suggest steps to manage the FLEXCAN driver and its configuration for smoothly switching from RUN to VLPR?
Thanks and Regards
Manuj Agrawal
Hi,
which driver do you mean? Assume SDK here...
If FlexCAN is using peripheral clock as PE clock still (CLKSCR=1) then it is enough to call FLEXCAN_DRV_SetBitrate() function to set new bitrates. it puts FlexCAN to freeze mode set bitrates and put module back to normal mode. There is an example to show this on https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K116-FlexCAN-VLPR-test-S32DS-ARM-2-2/ta-...
If PE clock must be changed then I think FLEXCAN_DRV_Deinit() should be called and after mode switch init all again with new setting. CLKSCR can be changed when module is disabled.
BR, Petr
Hi @PetrS
Thank you for your proposed solution. I think I can work with making the Peripheral Clock and PE Clock for an easy switch between RUN to VLPR.
Could you also please help me understand importance of PE and Module Clocks in FLEXCAN and which different functionalities in the FLEXCAN are governed by them separately?
Thanks and Regards
Manuj Agrawal
Hi,
refer to Table 27-9. Peripheral module clocking and chapter 55.5.10 Clock domains and restrictions of the reference manual.
BR, Petr