Hi,
I have a really basic question about FTM clock source selection. In RM table 27-8 it is written:
while in FTM_SC register the clock selection and prescaler is as follows:
The board is configured to run at system clock of 80 MHz and SPLLDIV1_CLK is set to 10 MHz (division factor of 16 from 160 MHz SPLL).
So my question is if according to the first snapshot the FTM clock source is selected to be SPLLDIV1_CLK and therefore it should run at 10 MHz, how does this relate to the second snapshot where the clock can be selected to be FTM Input clock? What is FTM Input clock in this case? Does it refer to the same 10 MHz SPLLDIV1_CLK?
In AN5303 it is mentioned that FTM clock source for counter can be either system clock, the fixed frequency clock or external clock. This apparently corresponds to the second snapshot above, but again how then the first snapshot is used to configure FTM clock source?
Still another question regarding the first snapshot. The second column for FlexTimer clock is SYS_CLK, while the forth column has other clocks like SPLLDIV1_CLK, FIRCDIV1_CLK, etc. Does the second column mention just the maximum possible clock? Or is there some other purpose?
I guess, all the above questions relate to some basic misunderstanding from my side of how FTM source clock (counter clock) is selected.
Ok, it seems the answer is given in the next diagram:
So the SPLLDIV1_CLK clock will be used by FTM counter only if the external clock source is selected for the FTM module. If the system clock is still selected then FTM counter will still run at 80 MHz despite the selection of SPLLDIV1_CLK in PCC module.
Please correct if the diagram has a different interpretation.
