Duration count value of IPWM in S32K3

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Duration count value of IPWM in S32K3

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dnewbe
Contributor III

Could you tell me why ActiveTime of IPWM is not understand value.

Below pic is my result when detect PWM signal that are each 1/1000, 250/1000, 500/1000, 750/1000, 999/1000 PWM signal.

Reference code is same as https://community.nxp.com/t5/S32K/S32K344-MCAL-IPWM-ICU-CAPTURE/m-p/1541889 example.

MCU is S32K312 and SDK is PlatformSDK_S32K3_2022_07_S32K312_M7 Ver 2.0.1.

dnewbe_0-1675225750540.png

The ration of ActiveTime is not understand each PWM duration.

 

1 Solution
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danielmartynek
NXP TechSupport
NXP TechSupport

Hello @dnewbe,

I'm sorry for the delay.

I made some changes in the project, and it works right now, plase find the modified project attached.

The main change was the edge polarity of the EMIOS IPWM channel.

It can't be set in the configuration tool of the ICU driver, so I set it by a direct write to the register in main().

IP_EMIOS_1->CH.UC[1].C |= eMIOS_C_EDPOL(1);

Overflow is an even when the MCL EMIOS_0_MasteBus0 overflows from 65535 to 0.

 

Regards,

Daniel

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dnewbe
Contributor III

I modify for your answer and I got wanted result.

 

My log of result is

PWM duty (1), period (1061) 

Bright Level (0) 

PWM duty (319), period (1061) 

Bright Level (30) 

PWM duty (637), period (1061) 

Bright Level (60) 

PWM duty (1060), period (1061) 

Bright Level (100)

 

Thanks danielmartynek.

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello @dnewbe,

There are two projects in the thread that you linked.

I don't knonw which one you use and what changes you made in it since then.

Can you share the project you have right now?

 

Double-check the EMIOs clock that the IPWM uses, it is possible that the counter overflows?

What is the period in which the counter overflows and what is the period of the PWM signal?

 

Thank you,

BR, Daniel

 

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dnewbe
Contributor III

I did refer code is nxf78987's code.

 

So I did test to caputure PWM signal from other Board that board generate PWM signal each 1kHz. I verify that signal with oscilloscope.

 

So I attach my project. Pls review my fault. 

 

Thaks

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello @dnewbe,

Thank you for the project, but I can't open the .mex file of the project.

Which RTD version do you use?

Can you use the latest version?

 

BR, Daniel

 

 

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello @dnewbe,

Could you increase the period of EMIOS_ICU_BUS_A in the MCL driver from the 1 you selected?

danielmartynek_0-1675782100941.png

So that the counter does not everflow?

 

Thank you,

Daniel

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dnewbe
Contributor III

Capture image of my setting is below.

dnewbe_1-1676010846038.png

The result is not change when each Prescaler and Alternate is DIVIDE_1.

 

And tell me overflow is what and how do I check ?

 

Test I did 

my board run 160 MHz is count PWM signal.

other board generate PWM signal each 1, 25, 50, 75, 99 duty of 1 KHz.

 

 

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1,308 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hello @dnewbe,

I'm sorry for the delay.

I made some changes in the project, and it works right now, plase find the modified project attached.

The main change was the edge polarity of the EMIOS IPWM channel.

It can't be set in the configuration tool of the ICU driver, so I set it by a direct write to the register in main().

IP_EMIOS_1->CH.UC[1].C |= eMIOS_C_EDPOL(1);

Overflow is an even when the MCL EMIOS_0_MasteBus0 overflows from 65535 to 0.

 

Regards,

Daniel