DMA write to ADC SC1

[Joey_van_Hummel]

Hi all,

We have > 8 ADC inputs that I want to sample, synchronized with FTM PWM INIT trigger.

We're using the PDB for this. But since we have a non-W S32K, I can't use back-to-back linking of CH0 and CH1 in the PDB.

I figured a solution would work where the DMA (triggered by ADC COCO) will rewrite ADC_SC1n in order to "link" more inputs, pulse-by-pulse. However it seems like writing to SC1n via DMA causes the PDB to be unable to trigger the ADC again (ES for the first channel becomes high).

Can anyone advice on how to achieve this?

Thanks,

Joey

[Joey_van_Hummel]

Hi Daniel,

Thanks for your reply. We are using an S32K142. Sadly the hardware is already definitive, and due to an oversight we have up to 11 channels on ADC0. Thus I would have liked to chain PDB0_CH0 and PDB0_CH1, but this requires PDB_BB_SEL[1] which is not available to us.

I was hoping to work around this by having the ADC trigger the DMA, which copies the results and then rewrites ADC-SC1n. The idea is that on the next INIT-trigger from the FTM, the remaining inputs are sampled.

Can you tell me if this should theoretically work? It seems like the PDB refuses to trigger ADC after writes to ADC->SC1 have occurred by the DMA. So I am doubting my strategy.

Kind regards,

Joey

[danielmartynek · Accepted solution]

Hi @Joey_van_Hummel,

I haven't testing it, but it should work.

Do you see any PDB error flags?

Can you check all the PDB and ADC registers after the DMA transfer?

Is there a chance you accidentally overwrite other ADC registers?

Regards,

Daniel

[Joey_van_Hummel]

Hi Daniel,

Thanks for your confirmation. It works now.

I had set ADC_SC1_AIEN of the last ADC channel, expecting that last channel exclusively to trigger the DMA. DMA copied then all results in one minor loop. But I re-read the RM and saw that every COCO triggers the DMA.

SC1 and the PDB were being altered while conversion was still active.

By setting DMA to move one result per minor loop, fixing my mistake, it now works as expected.

[danielmartynek]

Hi @Joey_van_Hummel,

Which S32K1xx part do you use?

CHIPCTL[PDB_BB_SEL] is supported not only on S32K14xW but S32K14x too.

The S32K14x parts allow chaining PDB0_Ch0 and PDB1_Ch0 back-to-back.

Regards,

Daniel