9 Bit SPI with DMA

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

9 Bit SPI with DMA

959 次查看
maximillion
Contributor II

I need to interface display with S32K142 MCU.

My project hardware has only 3 wires (CSX, SDA and SCL) from the display side. I have to use 3-wire 9-bit mode only. 

So I changed SDK for 3 wire SPI configuration according to reference manual. 

So this is my MasterInit Function and I configured SDO pin as Input/Output.

maximillion_0-1684853963295.png

And processor expert configuration is depicted below. 

maximillion_1-1684854061826.png

and this is my function 

maximillion_2-1684854105319.png

If so, I would like to know how to send 9 bits (1 D/C bit + 8 data bits) using SPI APIs. MasterGetTransferStatus function returned STATUS_BUSY.  Is there any error? 

How should I do that process. Thanks for answering. 

 

 

 

 

 

 

0 项奖励
回复
4 回复数

943 次查看
VaneB
NXP TechSupport
NXP TechSupport

Hi @maximillion 

Take a look at S32K 3-Wire SPI Drivers.

 

B.R.

VaneB

0 项奖励
回复

925 次查看
maximillion
Contributor II
The link you shared is not enough for me. I'm using S32SDK_S32K1xx_RTM_3.0.0 and when I look at the SDK what needs to be done for 3 wire communication is lpspi_pin_config_t and lpspi_data_out_config_t configuration. I made this configuration by modifying the SDK function. Does the S32SDK_S32K1xx_RTM_3.0.0 SDK version support this operation?
0 项奖励
回复

894 次查看
VaneB
NXP TechSupport
NXP TechSupport

Hi @maximillion 

Changes can be made to make the SDK functions support half-duplex.

As mentioned in the reference manual, to configure LPSPI in a half-duplex it is required to define CFGR1[PINCFG] as 01b (SIN is used for both input and output data) or 10b (SOUT is used for both input and output data), CFGR1[OUTCFG] as 1b to configure to tristate when LPSPI_PCS is negated and depending of the implementation for 2-bit transfers CFGR1[PCSCFG] as any value or for 4-bit transfers as 1b.

If we see from the SDK, LPSPI_SetPinConfigMode() needs to configure SDI as LPSPI_SDI_IN_OUT or SDO as LPSPI_SDO_IN_OUT and LPSPI_DATA_OUT_TRISTATE. These modifications would be for the register CFGR1 that I mentioned before.

For more reference, the post I shared earlier talks about the situation with no SDK.

0 项奖励
回复

833 次查看
maximillion
Contributor II

Hi @VaneB 

I have to use SDK so according to your last post my 3-wire SPI configuration is true right?

First of all, I used DMA for SPI configuration via Processor Expert. So I have a question about this topic. I used LPSPI_DRV_MasterTransfer() functions and LPSPI_DRV_MasterGetTransferStatus() to send SPI data. There are 4 parameters in LPSPI_DRV_MasterTransfer().MasterTransfer function, one of them is receiveBuffer but I am using 3-wire SPI so I gave NULL parameter for receiver buffer. Is this valid? If yes how can I get data from slave device via txBuffer. Is this possible for the RTM3.0.0 SDK?


Secondly, does the LPSPI_DRV_MasterTransfer function need to be modified to send and receive data on the same DMA TX channel? Because I choose No DMA for Rx channel via processor expert.

I am not totally clear about this sentence "when LPSPI_PCS is negated" what does that mean "PCS negated". Isnt peripheral chip select value low right?

0 项奖励
回复