we are currently facing an issue on S32G that ethernet communication on M7 side is broken

[Narasimha_manti]

we are currently facing an issue on S32G that ethernet communication on M7 side is broken, while CA53 core(s) are in reset or idle (probably WFI).

That effect is, however, not seen when cores of CA53 cluster are never started.
In our setup the PFE is only used by CA53 clusters, while M7 side is using GMAC.

Our observations:

1. If A53 core 0 just out of reset and stopped at first instruction by debugger. M7 cores communication with peripherals are affected (no CAN, serial and Ethernet communication). RTOS running in M7 is still active and running.
if the debugger is released, then system is back to working state.

2. If only M7 is active with no A53 cores running, then system works fine

At the current state we are actually looking for some support from NXP as we are kind of running out of ideas. Especially we cannot see a reason why just releasing 1 CA53 core out of reset and immediately breaking it with debugger should have an impact on M7 side which is not observed if that CA53 core is kept in reset.

[markusregner]

Hello Narasimha,

I need to ask you for two things on this particular case.

1. Please reach out direcly by mail to your respective NXP FAE regarding this case. If you are unsure about the contact check with your respective project manager who should have the NXP contacts.

2. Please don't use your private (gmail) address for such communications and instead always use the the one from your company.

We cannot provide support to registered persons with private addresses. I hope you are able to appreciate this.

-Markus