XGATEv3 breakpoint raising an access violation interrupt request to HCS12XE core

[gnaws]

Hallo,

I've been playing with the HCS12SXE XGATEv3 for a while now.

Currently, I'm facing this odd issue, where the XGATE code seems to run fine: I've set up a GPIO pin toggle to check and see if the XGATE ISR is entered and executed correctly, and on the scope I see the GPIO pin toggling fine.

However, if I place a breakpoint at any part of the XGATE ISR, the XGATE raises an access violation interrupt request (non-maskable) to the HCS12XE core and halts code execution.

The original codebase uses Processor Expert. XGATE capabilities are now being added in.

Any ideas, on what could be possibly happening? Everything else checks out - XGATE vector table is correctly set, memory sections and code/data is aligned correctly on even boundaries.

Thanks in advance.

[gnaws]

I'm actually not sure if the XGATE stops and enters debug mode.

• I can see that:

          XGATE:

               XGMCTL           = 0x00C3

               XGSPSEL         = 0x0

          HCS12XE:

               MPUFLG          = 0x0

               MPUSTAT0/1/2 = 0x0

• I can see is that control is passed to the HCS12XE core in a breakpoint in the routine "Cpu_ivVxsei".

• In the CPU vector table, the corresponding entry is:

          /* ISR name                                No.  Address Pri XGATE   Name            Description */

          &Cpu_ivVxsei,                         /* 0x0B  0xFF16   -        no       ivVxsei         unused by PE */

I should clarify the terminology I've used:

The manual 'MC9S12XE-Family Reference Manual Rev. 1.25', section 6.4.6 has a Table 6-2. "Exception Vector Map and Priority" (page 274).

From referring the table, I notice this particular interrupt/exception being triggered - and I think this is in fact colloquially referred to as the "XGATE software error vector":

          (Vector base + 0x0016): XGATE Access violation interrupt request

[HSW]

It sounds like you've configured the S12XDBG module to trigger an SWI interrupt whenever a XGATE breakpoint occurs. So you could check the following:

1. Is your vector table mapped in the correct location?
2. Does you SWI interrupt vector point to the correct ISR.
3. Did you configure the descriptors in the S12XMPU to grant access permission to the vector table and the SWI ISR.

[gnaws]

Heya HSW,

I've checked the vector table and the SWI ISR vector, they look good.

The MPU descriptors are configured by Processor Expert, and essentially the MPU should be disabled, from what I can tell. I'll have a closer look at those.

I've also worked through the application note here: http://www.freescale.com/files/microcontrollers/doc/app_note/AN3555.pdf, but I've not been able to detect the root cause of the error yet.

Bit more background detail: I have a standalone project, that essentially just exercises the XGATE. This works fine with breakpoints, stepping through the XGATE core etc. But integrating pieces of the code from the standalone project into the existing codebase has proved surprisingly trickly so far....

Anything else I could be missing out?