S12ZVMx12EVB PLL configuration with External crystal.

[ameykhatavkar]

Hi,

I am using S12ZVM evaluation board (S12ZVMx12EVB), and I am trying to configure PLL clock frequency as 100Mhz so that the Bus frequency will 50HZ.

For this I have set following register value considering crystal of 4MHz-

     setReg16(IVBR, 0xFFFEU); 

    /* Disable the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the

     * internal bus clock.

     * ECLKCTL: NECLK=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

    setReg8(ECLKCTL, 0x80U);   

    /*  System clock initialization */

    /* Procedure proposed by to setup PLL and Oscillator */

    /* For OSC = 4 MHz and Bus Clock = 50MHz, That is VCOCLK = 100MHz */

    /* Protection of the clock configuration registers from accidental overwrite

     * CPMUPROT: ??=0,??=0,??=1,??=0,??=0,??=1,??=1,PROT=0 */

    setReg8(CPMUPROT, 0x26U);            /* Disable protection of clock configuration registers */

    /* As we are using RTI, to do not halt RTI in staop mode we need to use Pseudo Stop Mode.

     * CPMUCLKS: PSTP=1 */

    clrReg8Bits(CPMUCLKS, 0x40U);

    /* System clocks are derived from PLLCLK, fbus = fPLL / 2.

     * CPMUCLKS: PLLSEL=1 */

    setReg8Bits(CPMUCLKS, 0x80U);        /* Enable the PLL to allow write to divider registers */

    /* PLL Clock = 100 MHz, divide by one *

     * If PLL is locked (LOCK=1),fPLL = fVCO/(POSTDIV + 1)

     * Here, fPLL = fVCO

     * CPMUPOSTDIV: ??=0,??=0,??=0,POSTDIV4=0,POSTDIV3=0,POSTDIV2=0,POSTDIV1=0,POSTDIV0=0 */

    setReg8(CPMUPOSTDIV, 0x00U);         /* Set the post divider register */

    /* Whenever changing PLL reference clock (REFCLK) frequency to a higher value

        * it is recommended to write CPMUSYNR = 0x00 in order to stay within specified

        * maximum frequency of the MCU

     * CPMUSYNR: VCOFRQ1=0,VCOFRQ0=0,SYNDIV5=0,SYNDIV4=0,SYNDIV3=0,SYNDIV2=0,SYNDIV1=0,SYNDIV0=0 */

    setReg8(CPMUSYNR, 0x00U);            /* Set the multiplier register */

    /* configure PLL reference clock (REFCLK) for usage with Oscillator

     * OSC = 4MHz divide by 2 (1+1) = 2 MHz, REFCLK range 1MHz to 2 MHz (REFFRQ[1:0] = 00)

     * CPMUREFDIV: REFFRQ1=0,REFFRQ0=0,??=0,??=0,REFDIV3=0,REFDIV2=1,REFDIV1=1,REFDIV0=1 */

    setReg8(CPMUREFDIV, 0x01U);          /* Set the divider register */

    /* enabled oscillator clock monitor reset

     * It must be done before setting OSCE bit in CPMUOSC register

     * CPMUOSC2: ??=0,??=0,??=0,??=0,??=0,??=0,OMRE=1,OSCMOD=0 */

    setReg8(CPMUOSC2, 0x02U);            /* Configure external oscillator options */

    /* enable external Oscillator, switch PLL reference clock (REFCLK) to OSC

     * CPMUOSC: OSCE=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ 

    setReg8(CPMUOSC, 0x80U);             /* Enable the oscillator */

    /* CPMUPLL: ??=0,??=0,FM1=0,FM0=0,??=0,??=0,??=0,??=0 */

    setReg8(CPMUPLL, 0x00U);             /* Set the PLL frequency modulation */

    /* multiply REFCLK = 2MHz by 2*(24+1)*2MHz = 100MHz

     * VCO range 80 to 100 MHz (VCOFRQ[1:0] = 11)

       * SYNDIV = 24

     * CPMUSYNR: VCOFRQ1=1,VCOFRQ0=1,SYNDIV5=0,SYNDIV4=1,SYNDIV3=1,SYNDIV2=0,SYNDIV1=0,SYNDIV0=0 */

    setReg8(CPMUSYNR, 0xD8U);            /* Set the multiplier register */

    /* Check The oscillator is qualified by the PLL*/

    while(CPMUIFLG_UPOSC == 0U) {        /* Wait until the oscillator is qualified by the PLL */

    }

But with this configuration Controller getting hang/going into exception. when I tried to change and configure the fPLL bellow 60Mhz it is working fine.

Please help me to resolve this issue.

Regards,

Amey

[lama]

Hi,

I am not able to check it now. I can do it tomorrow morning at work but could you please test:

void CPMU_Init(void)

{     

//ECLKCTL_NECLK = 0; //enable ECLK (BUSCLK at PP0 [J17.2, J23.1 - on the board]

//============================================================================

  //Default state after reset:

  // So after reset:

  //  CPMUOSC_OSCE == 0 =>  fref = firc1m = 1MHz

  //  CMPU_PLLSEL == 1 =>  fpll = fref / 4 =   while not locked

  //                             = 1MHz / 4 = 250kHz     

  //                  then  fpll = 2 * fref *(syndiv+1) / (postdiv + 1) =      

  //                             = 2 * 1MHz *(24    +1) / (3       + 1) =

  //                             = 50 / 4 = 12.5MHz

  //                        fbus = fpll / 6.25MHz                     

//============================================================================

// PLL setup 50 MHz BUSCLK from 4 MHz

CPMUREFDIV   = 0x01;  // fref = fosc/(refdiv+1) = 4 / (1 + 1) = 2MHz             00_00_0001

CPMUSYNR     = 0xD8;  // fVCO = 2 * fref * (SYNDIV + 1) = 100 => SYNDIV=24d=18h  11_011000

CPMUPOSTDIV  = 0x00;  

CPMUOSC_OSCE = 1;

while(CPMUIFLG_UPOSC == 0){ __RESET_WATCHDOG(); }     

CPMUCLKS_PLLSEL = 1; // PEE  

}

Best regards,

Ladislav

[ameykhatavkar]

Hi Ladislav,

Thanks for your comments.

As I mentioned in my last mail, It is working fine up to 60 MHz.But when I am trying to set the frequency above 60~70MHz.

It giving the problem as I mentioned.

For the more clarification mentioning that, I am using the PE Micro's Multilink Universal FX debugger and connected to the EVB through the BDM.

The EVB is powered up by the supply of 5V from debugger.

Regards,

Amey

[lama]

Hi,

I have used universal multilink and rewritten step by step your code to my form:

IVBR         = 0xFFFEU;

ECLKCTL      =   0x80   ;

CPMUPROT     =   0x26 ;   

CPMUCLKS    &= (~0x40)  ;   

CPMUCLKS    |=   0x80   ;

CPMUPOSTDIV  =   0x00 ;   

CPMUSYNR     =   0x00 ;   

CPMUREFDIV   =   0x01   ;

CPMUOSC2     =   0x02   ;

CPMUOSC      =   0x80   ;

CPMUPLL      =   0x00   ;

CPMUSYNR     =   0xD8 ;   

while(CPMUIFLG_UPOSC == 0U) {        /* Wait until the oscillator is qualified by the PLL */

    }

The setup look to be OK on the first view. I have just change ECLKCTL regster setup to be able to see BUSCLK at the ECLK pin and everything is OK. Could you check reset pin whether there is no accidental behavior.

Ladislav

[ameykhatavkar]

Hi Ladislav,

Thanks you. Also I have confirmed the same.

But I have seen the debugger(PE Multilink Universal FX), is not communicating with the target at same time(at 100MHz) and I am unable to debug the things  or step by step execution using code warrior 10.06 and Multilink Universal FX debugger,

Please help me resolve it.

Regards,

Amey

[MJW]

Hello,

There are sometimes problems caused by running the debugging interface with bus-clock speeds close to the limit the Multilink cables can actually support on the BDM interface (the limit is 50MHz, IIRC).

To resolve this the BDC interface can be set to use the fixed IRC clock (1MHz) instead of the bus-clock, so that the communication with Multilink is not affected by changes in the clocking set-up.

This is how to do it in CW 10.6:

1. Go to "Run/Debug settings" in your project's "Properties".
2. Select the Multilink connection from the list presented and click on "Edit".
3. In the "Main" Tab, "Target settings" click on the "Edit..." button next to the "Connection:" field.
4. Uncheck the option "Use Bus Clock as Debug Controller (SIBDC) Clock Source {Default = Checked}" under "Connection" -> "Additional Options".
5. Click on "Ok" in each of the three open windows.

One thing to be aware of: While this setting might solve debugging problems caused by high bus-clock speeds, it will also slow down the initial download of the program code a little bit.

HTH,

MJW

[ameykhatavkar]

Hi MJW,

Thank you for your comment.

It clear my concern.

Regards,

Amey