S12XS - interrupt controlled hardware finite state machine

[JadhavAj]

Hi,

I read following statement in some forum,

"current controllers and flash devices have an internal interrupt

controlled hardware finite state machine to control the timing of the erase /

write operations."

I am writing flash driver for S12XS controller, I did not find any reference in datasheet where above statement can be proven.

Any pointers for same?

Thanks.

Regards,

 Ajay

[kef]

If you compare S12/S12X flash program/erase procedure to say MC912D60A flash prograam/erase, then you will note that S12/S12X do have program/erase finite state machine and D60A doesn't have such machine. Programming D60A user software has to set PGM bit, write aligned word to flash to select row of flash to be programmed, wait for 10us, set flash programming voltage enable bit, wait 5us, write data, wait for word program time, 30-40us, repeat write-wait until whole row is programmed, finally clear PGM bit, wait 5us and clear HVEN bit. In contrast, S12/S12X have flash programming state machine so that we just write a flash command and flash data and just wait until CCIF is set, or until CBEIF is set and we can write another command to flash controller. In D60A we had to follow specific timing precisely, interrupts had to be disabled, else we could overexposure high voltage applied to flash and damage the flash. S12/S12X flash state machine easied it a lot.