Hi!
I'm trying to map RAM and EEPROM on my new project. I'm using S12A128, and I couldn't find any documentation on those registers. I've got it for the S12A256, but not for the 128. I seaarch the web and I found that those belongs to the HCS12 Core, and I read the "HCS12 V1.5 Core User Guide Version 1.2". RAM mapping is what confuse me the most.
Please, correct me if I'm wrong:
According to the document above:
INITEE
| EE15 | EE14 | EE13 | EE12 | EE11 | xxxx | xxxx | EEON |
bits EE15 to EE11 determine the upper five bits of the base EEPROM address, so if I want EEPROM at:
1) 0x0000, then INITEE = 0x01
2) 0x2000, then INITEE = 0x21
right?
INITRM
| RAM15 | RAM14 | RAM13 | RAM12 | RAM11 | xxxx | xxxx | RAMHAL |
bits RAM15 to RAM11 determine the upper five bits of the base RAM address and RAMHAL determine align to 0x0000 or 0xFFFF
Alignment is what confused me. After reset INITRM = 0x09... so where RAM would be at?
According to MC9S12A128A (here), it would be at 0x0000...... but according to MC9S12DP256 (here) it would be at 0x1000.... If INITRM and INITEE are HCS12 Core registers... then wouldn't it be the same for both derivatives?
已解决! 转到解答。
You got INITEE right.
RAMHAL is relevant for RAM blocks with size not equal to 2^N :smileyhappy:. This applies only to 12kB RAM block. RAMHAL aligns 12kB RAM block towards closer 2^N boundary. With bits RAMx bits set to 0, you may map 12k RAM either to 0..2FFF or to 1000..3FFF. With RAMx bits set to 0x40 you may map 12k block either to 0x4000..0x6FFF or to 0x5000..0x7FFF. Etc.
There is some AN (sorry, don't remember which one), which suggested initializing INITRM with 0x39 for all S12D/S12A variants, so that RAM is mapped on all 64/128/256/512 variants with top address of RAM at 0x3FFF. This makes sense, especially if you want compiled code compatibility to allow you to replace D64 with all bigger 128's and 256's without recompile, when smaller ones are out of stock.
You got INITEE right.
RAMHAL is relevant for RAM blocks with size not equal to 2^N :smileyhappy:. This applies only to 12kB RAM block. RAMHAL aligns 12kB RAM block towards closer 2^N boundary. With bits RAMx bits set to 0, you may map 12k RAM either to 0..2FFF or to 1000..3FFF. With RAMx bits set to 0x40 you may map 12k block either to 0x4000..0x6FFF or to 0x5000..0x7FFF. Etc.
There is some AN (sorry, don't remember which one), which suggested initializing INITRM with 0x39 for all S12D/S12A variants, so that RAM is mapped on all 64/128/256/512 variants with top address of RAM at 0x3FFF. This makes sense, especially if you want compiled code compatibility to allow you to replace D64 with all bigger 128's and 256's without recompile, when smaller ones are out of stock.
I think the foolowing should clarify a bit RAMHAL.
On targets with 2k RAM, RAM is mappable to 2k boundary 0, 0x800, 0x1000, ...
On targets with 4k - to 4k boundary 0,0x1000, 2000, ...
8k - 8k boundary ...
16k - 16k boundary
For all blocks mentioned above RAMHAL doesn' affect anything. But on targets with 12k RAM, RAM is mappable to 16k boundary and adjusted within 16k boundary either down or up. So you map 12k block as 16k block to 0, 0x4000, 0x8000.., and adjust missing 4k hole with RAMHAL either up or down. Hope it's clear
Thanks kef!
Your second post clarify me a lot!
I think I'll map RAM as suggested by the AN you mentioned INITRM = 0x39, so I won't deal with it any time I change the derivative.
Thanks again!
Best Regards!