MC9S12ZVCRMV1 Conflicting Register Defaults (MODRR0)

[braxton]

In the MC9S12ZVC-Family Reference Manual and Datasheet (accessible here: https://www.nxp.com/products/processors-and-microcontrollers/additional-mpu-mcus-architectures/s12-m...)

It is stated in section 2.3.2.1 Module Routing Register 0 (MODRR0) that MODRR0 has a default reset state of 0b00000000. It states below, in Table 2-4. MODRR0 Routing Register Field Descriptions:

bits 7-6     |     IIC0RR1-0     |     Module Routing Register — IIC0 routing
11 Reserved
10 SCL0 on PT1; SDA0 on PT0
01 SCL0 on PS1; SDA0 on PS0
00 SCL0 on PJ1; SDA0 on PJ0

bit 4     |     SCI0RR     |     Module Routing Register — SCI0 routing
1 TXD0 on PS1; RXD0 on PS0
0 TXD0 on PJ1; RXD0 on PJ0

This suggests that in a default reset state PJ0 and PJ1 both have two conflicting signals routed. Obviously in real world use we will be manually defining MODRR0 to avoid these sorts of conflicts, but is this the correct default state? On reset are pins PJ0 and PJ1 in some unknown state, or are they defaulted to either IIC or SCI?

EDIT: Mystery solved, see my reply below.

[braxton · Accepted solution]

Aaaaand I found the answer: pins PJ0 and PJ1, as all pins, have a list of signal priorities:

and SCI is prioritized first, so if SCI and IIC are both set to PJ0/PJ1, SCI should be the actual signal on the pins.