HC(S)12: How to do clock stretching from IIC slave?

[pittbull]

Hello,

I implemented an IIC slave according to the flow chart in S12IICV2.pdf (page 39). The code runs entirely from an ISR. In the box "Read data from IBDR and store" I want to do clock stretching to slow down the master if memory becomes low. Anyone knows how to do this?

Thanks in advance,
pittbull

[bigmac]

Hello pittbull,

Perhaps it is a case where clock stretching will be accepted during master mode, but cannot actually be generated whilst in slave mode - I am not sure.  As an alternative approach, maybe your master transmissions can be satisfactorily slowed by use of "handshaking" between byte transfers, by the slave delaying the release of the SCL line following ACK.

Regards,
Mac

[pittbull]

Hello Mac,

Mac wrote:
>> As an alternative approach, maybe your master transmissions can be
>> satisfactorily slowed by use of "handshaking" between byte transfers,
>> by the slave delaying the release of the SCL line following ACK.

Yes, that's what I mean. From the docs I found that SCL is released after IBDR is read or written, but I think that my ISR won't run correctly if I only leave out the 'Read from IBDR' (Sorry, haven't not yet tested it). Maybe the ISR is called again a few cycles later to give me another chance to release SCL? I don't think S12 IIC is that user-friendly

Message Edited by pittbull on 2006-07-26 04:13 AM