Double buffer on SPI communication with HCS12X ?

[bipp]

Hello,

We have a project where we use SPI protocol to allow the communication between two microcontrolers. We use a MC9S12XET256 as slave.

On this last microcontroller, the SPI data are loaded on transmission interruptions (Rx and Tx interruptions are allowed). What we saw with the SPI analyser, is we have a shift of two bytes... We understand well the first one, it's because we loaded our first byte in the transmitter buffer after receiving the first byte from the master. But we can not explain the second shift...

After reading the datasheet, it is as we have a data buffer between SPI Data Register and Shifter... Can you confirm this behaviour?

[RadekS · Accepted solution]

Hi Micka,

1. Could you please clarify the SPI bus configuration?

The interesting is mainly setting of SPI Clock Phase Bit (CPHA) and Transfer Width (XFRW).

The SS (CS) pin must go to a high level at the end of every transfer when CPHA=0.

Please check also minimum leading time before the first SCK edge, minimum trailing time after the last SCK edge and minimum idling time between transfers (minimum SS high time).

The slaves SPIDR register should be already written at least half SCK cycle prior new transfer begins.

So, if two bytes are transferred without any gap for SPI command processing or when we do not handle SS signal between these transfers (only when CPHA=0), two bytes shift will be probably a result.

2. You should be also careful with TX interrupt.

This is a typical issue: When we enable TX interrupt during SPI initialization, TX ISR will be executed “immediately” since SPTEF=1 by default and TX buffer will be filled with some “dummy” value. So, there is at least one byte additional shift in compare with expected result.

So, correctly we should initialize SPI with disabled TX interrupt. When we receive SPI command, we should write the first byte into SPIDR register and enable TX interrupt for rest of the message. We will disable the TX interrupt when we send the last byte from the message into SPIDR register.

I hope it helps you.

Have a great day,
RadekS

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[bipp]

Hi Radek,

Thank for your answer.

To begin my SPI bus configuration: CPHA=1, CPOL=0 and XFRW=0.

To be sure you well understand my problem, this is a screenshot of the behavior seen.

The bus1 corresponds to the SPI slave bus, and bus2 to the SPI master bus.

The value "0x55" is the value we load each time in the SPI data register when the slave (or master) has nothing to transmit. So we would like to understand why the value "0x5F" is not immediatly transmitted on the MISO after receiving a clock signal.

Do you think it is linked to the problem with the Tx interrupt you talked about? Indeed, this interrupt is always activated... But I tried by always deactivating the Tx interrupt and I observed exatcly the same behavior...

[bipp]

Excuse me. I reboot my board with th TX interrupt always deactived and this unexpected byte disapear. So it's maybe the problem... I am going to keep an eye on this... Thank you for your help :smileyhappy:

[RadekS]

Hi Micka,

Thank you for more details and clarfication.

You are welcome.

I am glad that it works now.

Best Regards,
RadekS