t1042 espi transactions with TPM

[zwg132883]

Hi,

We have a TPM device(SLM9670) connected to T1042 by SPI bus. From tpm driver, T1042 send multi-bytes(0x80-0xd4-0x00-0x00) to TPM, then T1042 get 0x01 from SPI iobuf, which is correct. Next step, CPU need to continue get next byte from TPM device, but CPU release the CS at previous transaction. Looks cs_change=0 does not take effect during SPI transaction. How to keep CS holding low during the whole SPI transactions? thanks.

TPM driver logic:

1st transaction:
io-buf=0x80-0xd40-0x00-0x0
spi_xfer.len = 4
spi_xfer.cs_change = 1
spi_message_init(&m)
spi_message_add_tail(&spi_xfer, &m)
ret = spi_sync_locked(phy->spi_device, &m)
get io-buf[3]=0x01         <- so far so good

2nd transaction:
spi_xfer.cs_change = 0
spi_xfer.len = transfer_len
spi_xfer.delay_usecs = 5
spi_message_init(&m)
spi_message_add_tail(&spi_xfer, &m)
ret = spi_sync_locked(phy->spi_device, &m)
get incorrect data from io-buf

[yipingwang]

Please refer to the following update from the AE team.

According of SPI protocol, for SPI transaction, that included enable CS, transfer data.
If the transfer is not completed, the CS should not be disabled.

Maybe Customer can debug the cs_change status duration the whole transfer.