We created a board with the MPC8349ECVVAJFB processor on it, but the signal
LGTA was not connected or pulled up. Can we fix this by setting the LBCR( LPBSE ) bit to 1?
We will be using the GPCM with BR0 and OR0 to load flash at power up boot. Currently
the board runs code then faults at the same address some times. Below quoted from
MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1.
"14 LPBSE Enables parity byte select on LGTA/LGPL4/LUPWAIT/LPBSE signal.
0 Parity byte select is disabled. LGTA/LGPL4/LUPWAIT/LPBSE signal is available for memory control as
LGPL4 (output) or LGTA/LUPWAIT (input).
1 Parity byte select is enabled. LGTA/LGPL4/LUPWAIT/LPBSE signal is dedicated as the parity byte select
output, and LGTA/LUPWAIT is disabled."
Roger Plantowsky
GET Engineering
(619)443-8295
Yes the GPCM ignores LGTA/ LPBSE pin state if the LBCR( LPBSE ) bit is set. But it fixes problem for sure only if you can set this bit before GPCM using. On reset this bit is cleared. The I2C boot sequencer can set this bit. Of course if the first instruction read from the boot flash set this bit the probability of the fail is decreased.
Serguei,
Thanks for your comments.
The software group thinks that the BDI3000 debugger can set this
bit before the first instruction read. Is this correct?
Roger Plantowsky