dpl file error for LS1088

[ferditekce]

Could any provide the example dpl file for LS1088a with RGMII PHY on EC1 interface?

Our serdis configuration is :

Using SERDES1 Protocol: 21 (0x15)
Using SERDES2 Protocol: 0 (0x00)

we have this error when apply the default dpl file or attached dpl file.

=> fsl_mc apply DPL 0x80300000

fsl-mc: Deploying data path layout ... WARNING: Firmware returned an error (GSR: 0x3f)

[yipingwang]

Hello Ferdi Tekce,

I have verified your DPL file, it was applied successfully on my LS1088ARDB board.

=> tftp 0x80300000 b25805/ls1088ardb/dpl-eth.0x15_0x00.dtb
=> fsl_mc apply DPL 0x80300000
fsl-mc: Deploying data path layout ... SUCCESS
=>

I attached MC and DPC images from LSDK 1909 release, please apply them at 0x00A00000 and 0x00E00000 on QSPI flash separately.

Thanks,

Yiping

[ferditekce]

Firstly, thanks for the answer! What is serdes configuration in rcw file. When I change the serdes configuration as follows, I have this error.

fsl_mc apply DPL 0x80300000

fsl-mc: Deploying data path layout ... WARNING: Firmware returned an error (GSR: 0x3f)

SERDES1 Protocol: 21 (0x15)

SERDES2 Protocol: 0 (0x00)

[yipingwang]

Please refer to serdes configuration on LS1088ARDB, please try the whether this problem remains with the following serdes configuation.

Reset Configuration Word (RCW):
       00000000: 4000541c 00000040 00000000 00000000
       00000010: 00000000 000a0000 00300000 00000000
       00000020: 034011a0 00002580 00000000 00000040
       00000030: 0000005b 00000000 00002403 00000000
       00000040: 00000000 00000000 00000000 00000000
       00000050: 00000000 00000000 00000000 00000000
       00000060: 00000000 00000000 00000011 000009e7
       00000070: 44110000 00107777
VID: Core voltage after adjustment is at 1025 mV
DRAM:  7.9 GiB
DDR    7.9 GiB (DDR4, 64-bit, CL=15, ECC on)
       DDR Chip-Select Interleaving Mode: CS0+CS1
Using SERDES1 Protocol: 29 (0x1d)
Using SERDES2 Protocol: 19 (0x13)