ddr3 deskew feature for P1020

[hk1]

Let me ask one basic question. I may misunderstand something.

In phgl_s_a0009748696_1-2279788.pdf, I could not understand Table 23.
There is same description in other QorIQ product datasheet.

If P1020 don't have deskew feature, the tolerance could be 10ps more or less.
If P1020 has that feature, 390ps is possible but I cannot find any
deskew, ddrphy training, eye centering word in datasheet.
P1020 has that feature?

If P1020 has,
How about write MDQ to MDQS deskew?
How about command or address to CK deskew?

[Irene]

I don't quite understand your questions.  So the design checklist that you are referring to is used as a guide to use when designing your P1020 based custom board.  Are designing a board based on the P1020? 

[hk1]

Hi Irene,

Thank you for replying.

Our initial version is designed with P1020 long time ago.
There is a plan for version up but not exact plan yet.
I change my question.

What I want to know is about ddr-phy training, i.e. read/write leveling and deskewing.
The AN below is close to my quesiton.
https://www.nxp.com/docs/en/application-note/AN4466.pdf

I want to know the current status which MCU (i.MXxx,P1020,P2020,P5040...) support the feature
for which ddr (ddr3,ddr4,ddr5,lpddr3,lpddr4,lpddr5).

Regards,