We are bringing up a custom board based on the LS2088ARDB. We replaced the DIMMs with AS4C512M16D4-75BCN from Alliance Memory and developed DDR initialization code using the QorIQ Configuration tool.
When the target initialization file runs, it gets to this subroutine and does not exit.
def A009803_Erratum():
DDR_BASE = 0x01080000
# 1. Configure the DDR registers as normal with parity enabled
CCSR_LE_M(0x01080114, 0x00401050 | 0x00000020)
# 2. Set ERR_DISABLE[APED]
CCSR_LE_M(0x01080E44, 0x00 | 0x00000100)
# 3. Set DDR_SDRAM_CFG[MEM_EN]
CCSR_LE_M(0x01080110, 0x65200000 | 0x80000000)
# 4. Poll for DEBUG_2[30] to be set
while True:
time.sleep(0.2)
debug_2_value = CCSR_LE_D(DDR_BASE + 0xF04)
if debug_2_value & 0x2 != 0:
break
# 5. Clear ERR_DIS[APED]. Parity checking is now enabled
CCSR_LE_M(0x01080E44, 0x00 & (0xFFFFFFFF ^ 0x00000100))
What would cause "if debug_2_value & 0x2 != 0:" never to resolve to true?
I have submitted an NDA request to get access to the errata sheet for the processor.
I have also noted that the generated code references several registers which are not mentioned in the QorIQ LS2088A Reference Manual, Rev. 1, 09/2020. Is there any better documentation for the DDR configuration registers?
I have attached the generated python file. We have merged this file into the target initialization file and adjusted the CSx_BNDS registers to reflect our memory map.
