SDRAM Clocking!

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SDRAM Clocking!

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qammarabbas
Contributor IV

Hi,

I am interfacing 8 DDR3L devices with T1042. The external pin description of T1042 DDR Controller mentions 2 clocks MCK0 and MCK1. Why is there a second clock? Can't i drive all 8 SDRAM devices with a single clock only? 

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ufedor
NXP TechSupport
NXP TechSupport

> Can't i drive all 8 SDRAM devices with a single clock only?

Driving all SDRAM devices connected to the same chip-select with a single/same MCKn is a must.

Please refer to the AN3940 - Hardware and Layout Design Considerations for DDR3 SDRAM, Table 1. DDR3 designer checklist:

"46. Ensure one clock pair is used for each chip-select. The clock pair should follow the address/command/control signal groups in fly-by topology."

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ufedor
NXP TechSupport
NXP TechSupport

> Can't i drive all 8 SDRAM devices with a single clock only?

Driving all SDRAM devices connected to the same chip-select with a single/same MCKn is a must.

Please refer to the AN3940 - Hardware and Layout Design Considerations for DDR3 SDRAM, Table 1. DDR3 designer checklist:

"46. Ensure one clock pair is used for each chip-select. The clock pair should follow the address/command/control signal groups in fly-by topology."

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