QSPI boot on LS1043A

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QSPI boot on LS1043A

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j_wallace
Contributor II

Hi Experts,

According to the following document : https://community.nxp.com/docs/DOC-102040

1) Could you please confirm that the byte swap process is required on LS1043A too when booting from QSPI?

2) If byte swap is required what does the following warning from QCVS mean?

pastedImage_1.png

Best Regards.

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6 Replies

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yipingwang
NXP TechSupport
NXP TechSupport

Hello j_wallace,

Quad serial peripheral interface is big-endian, byte swapping is required.

QSPI RCW and u-boot images generated in Yocto or FlexBuild SDK have already been swapped, could be used directly by users, no need extra byte-swap manual step. QSPI RCW image is swapped by Yocto/FlexBuild recipe/script. In the recent released u-boot source code, the swapped QSPI u-boot image is generated directly.

If you use QCVS tool to generate QSPI RCW, you need to do swapped manually.

I suggest you use "rcw" package provided in SDK to generate QSPI RCW, it is more convenient,


Have a great day,
TIC

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j_wallace
Contributor II

OK. Thanks a lot.

I'am using QorIQ SDK 2.0. and bringing-up a custom board. So I have to adapt the RCW using QCVS but having some troubles.

Our board has a L1043A Silicon rev 1.1 while It looks like QCVS supports  only  Silicon rev 1.0. Is there a QCVS version supporting Silicon rev 1.1?

Best Regards.

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addiyi
NXP Employee
NXP Employee

No differences between rev1.0 and rev 1.1 from QCVS point of view. This is the reason for having only rev 1.0 available. Also, to have the RCW swapped generated by QCVS it is enough to select RCW Source QSPI and you will see in Generated_Code folder the swapped binary.

Adrian

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j_wallace
Contributor II

Hello,

Thanks for your reply.

In QCVS I imported LS1043A-QDS RCW file generated in Linux SDK 2.0 and tried to adapt it to our board but the board still does not boot.

Now I downloaded the last version of QCVS (2018-01) which seems to have default RCW to start from. Maybe I should start from this default RCW instead of QDS RCW since our board is different.

SERDES protocol = 3558

SDRAM = MT40A512M16JY-083E IT:B   (We have to DDR4 SDRAM chip for total 1GB memory size )

I'started from u-boot for LS1043ARDB (as QDS is not for sell) and adapt it with QSPI device definition in device tree and ls1043ardb.h.

As complexity is increasing, I'am trying to validate the RCW and the boot with minimal code. So I used u-boot-spl.bin (SD boot SPL) for which I chaged the link address CONFIG_SPL_TEXT_BASE=0x40010000.I did the same on RDB board with link addresse 0x60100000 and it worked fine in parallel NOR flash. I'm using u-boot from DENX u-boot-qoriq GIT tree.

1) Is CodeWarior TAP abble to debug code in QSPI NOR flash ? (s25fs128s)

3) Is CodeWarior TAP abble to initialize DDR controller with our SDRAM

2) Do you have minimal software like uart example I may flash to validate the boot process instead of whole u-boot?

Currently I have Lauterbach Trace32 but it cannot initialize DDR by itsel but it use u-boot-spl then load code to SDRAM...(!!!)

Best regard.

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j_wallace
Contributor II

Sorry for typo error ... I mean our board has two SDRAM chip of 512 MB (i.e. memory size = 1GB)

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yipingwang
NXP TechSupport
NXP TechSupport

Hello j_wallace,

You could refer to the following procedure to generate QSPI RCW in QorIQ SDK 2.0.

$ bitbake rcw -c cleansstate

$ bitbake rcw -c patch

Go to RCW source code folder, you could refer to LS1043AQDS QSPI RCW for reference, please refer to build_ls1043aqds/tmp/work/ls1043aqds-fsl-linux/rcw/git-r0/git/ls1043aqds/RR_FQPP_1455/rcw_1600_qspiboot.rcw to do modification according to your custom board.

Then regenerate RCW binary file

$ bitbake rcw

The generated RCW binary file is also in the folder build_ls1043aqds/tmp/work/ls1043aqds-fsl-linux/rcw/git-r0/git/ls1043aqds/RR_FQPP_1455/.


Have a great day,
TIC

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