LS1046A with Flash Nand

[arnaudcsug]

I'm trying to figure out on how to attach two 2Gb NAND flash to a LS1046a and to have Linux detect them as MTD devices. I have read in the §22.5.5 of the Reference Manual it is stated that device is not accessed directly, instead a SRAM buffer is used.

The relevant section of the device tree I use is:

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
    
	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
			0x1 0x0 0x0 0xfe800000 0x0010000>;
	status = "okay";
	
	nand@0,0 {
		#address-cells = <1>;  
		#size-cells = <1>;     
		compatible = "fsl,ifc-nand";
		reg = <0x0 0x0 0x10000>;
		status = "okay";
	};

	nand@1,0 {
		#address-cells = <1>; 
		#size-cells = <1>; 
		compatible = "fsl,ifc-nand";
		reg = <0x1 0x0 0x10000>;
		status = "okay";
	};
};

And here is the mdparts option in the kernel command line:

mtdparts=7e800000.flash:-(my_nand)

Here are some questions:

1. How to set the flash nand memory size ? Shall I use the device tree ranges option, or specify it in the mtdpart command line option ?
2. Is the sample device tree above correct for configuration of two nand devices ?
3. Is it possible to merge the two nand 2GB devices to have only a single 4GB mtd device ?

[arnaudcsug]

Eventually I found out. As stated in the documentation, the NAND flash is accessed through a buffer of 64KiB, and those 64KiB is the memory space in the IFC range. Therefore the second NAND can be located at CONFIG_SYS_NAND_BASE + 0x10000.

The board configuration:

#define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE, \
					  (CONFIG_SYS_NAND_BASE + 0x10000) }
#define CONFIG_SYS_MAX_NAND_DEVICE      2

#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR + 0x10000
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif

Even if U-Boot seems not to use the device tree for IFC NAND, we needed to update it for Linux:

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
		  0x1 0x0 0x0 0x7e810000 0x00010000>;
	status = "okay";
	
	nand@0,0 {
		compatible = "fsl,ifc-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x0 0x0 0x10000>;
	};

	nand@1,0 {
		compatible = "fsl,ifc-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x1 0x0 0x10000>;
	};

};

[yipingwang]

1. You need to specify the memory size as the following.

mtdparts=7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)

2. In "ranges" definition, the first item is correct, address "0xfe800000" in the second item is incorrect. Please refer to "System memory map" in LS1046ARM", IFC region should be "0x6000_0000 - 0x7fff-ffff", you need to use the address in this range.

3. You need to define two NAND device at CS0 and CS1 separately.

[arnaudcsug]

Thanks for the reply,

2.a. From the documentation the IFC region is divided in two regions, one of 512MB at 0x00_6000_0000 and a second one of 3.5GB at 0x06_2000_0000.

If we want the first 2GB NAND connected on CS0 cover the first region and the other 2GB NAND connected on CS1 cover the second region, we would write:

ranges = <0x0 0x0 0x0 0x60000000 0x00010000
          0x1 0x0 0x06 0x20000000 0x0010000>;

 Is this correct ?

2.b. From the documentation, the read and write accesses to IFC banks are performed through a buffer SRAM. It is not clear to me whether the last value shall be the size of the NAND device or the size of the SRAM buffer. Which one is the right one ?

2.c. In case both NAND chips have to be in the first IFC region, how can be calculated the starting address of the second 2GB NAND ?

[nfj]

Hey @arnaudcsug ,

  Not sure if you already saw the following posts, but they were informational to me: LS1043 link | T1042 link.  I know the T1042 is a different device, but the IFC seems to operate in a similar manner.

  Even with that information, I'm still a little confused as well as we are apparently supposed to also change a u-boot header file, as stated in a response to the first link:

"You need to modify NAND flash IFC controller timing configuration and block size in u-boot source code include/configs/ls1043argw.h." 

They don't go on to say exactly how to do that when it comes to adding a second chip select for the NAND interface.

  I'd be interested to hear if you figure it out.

Thanks,

-Nate J